Abstract: Methods are presented of forming sub-lithographic patterns using double exposure. One method may include providing a photoresist layer over a layer to be patterned; exposing the photoresist layer using a first mask having a first opening; developing the photoresist layer to transfer the first opening into the photoresist layer, forming a boundary in the photoresist layer about the transferred first opening that is hardened; exposing the photoresist layer using a second mask having a second opening that overlaps the boundary; and developing the photoresist layer to transfer the second opening into the photoresist layer, leaving the boundary, wherein the boundary has a sub-lithographic dimension.

Abstract: An electrical fuse and a first dielectric layer thereupon are formed on a semiconductor substrate. Self-assembling block copolymers containing two or more different polymeric block components are applied into a recessed region surrounded by a dielectric template layer. The self-assembling block copolymers are then annealed to form a pattern of multiple circles having a sublithographic diameter. The pattern of multiple circles is transferred into the first dielectric layer by a reactive ion etch, wherein the portion of the first dielectric layer above the fuselink has a honeycomb pattern comprising multiple circular cylindrical holes. A second dielectric layer is formed over the circular cylindrical holes by a non-conformal chemical vapor deposition and sublithographic cavities are formed on the fuselink. The sublithographic cavities provide enhanced thermal insulation relative to dielectric materials to the fuselink so that the electrical fuse may be programmed with less programming current.

Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

Abstract: Methods of fabricating transistors, semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, and forming a gate over the gate dielectric. Sidewall spacers are formed over the gate dielectric and the gate, the sidewall spacers comprising germanium oxide (GeO or GeO2).

Abstract: A lithography system with a stray light feedback system is disclosed. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.

Abstract: A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

Abstract: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w<d. Each single unit polymer block of the present invention is embedded in a polymeric matrix and can be selectively removed against the polymeric matrix to form a single opening of the diameter w in the polymeric matrix inside each of the mask openings. Sub-lithography feature patterning can then be conducted in the device structure using the single openings of diameter w.

Abstract: The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

Abstract: A stray light feedback system and method for a lithography exposure tool. The stray light feedback helps control critical dimension (CD) within a stray light specification limit. A stray light dose control factor is calculated as a function of the stray light measured in the exposure tool and the sensitivity of the resist. The stray light dose control factor is used to adjust the exposure dose to achieve the desired CD. The stray light may be monitored, and if a threshold level of stray light is reached or exceeded, the use of the exposure tool may be discontinued for a particular type of semiconductor product, resist, or mask level, until the lens system is cleaned.

Abstract: A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line.

Abstract: An anti-reflective coating material, a microelectronic structure that includes an anti-reflective coating layer formed from the anti-reflective coating material and a related method for exposing a resist layer located over a substrate while using the anti-reflective coating layer provide for attenuation of secondary reflected vertical alignment beam radiation when aligning the substrate including the resist layer located thereover. Such enhanced vertical alignment provides for improved dimensional integrity of a patterned resist layer formed from the resist layer, as well as additional target layers that may be fabricated while using the resist layer as a mask.

Abstract: A method of forming shallow trench isolation (STI) regions for semiconductor devices, the method including defining STI trench openings within a semiconductor substrate; filling the STI trench openings with an initial trench fill material; defining a pattern of nano-scale openings over the substrate, at locations corresponding to the STI trench openings; transferring the pattern of nano-scale openings into the trench fill material so as to define a plurality of vertically oriented nano-scale openings in the trench fill material; and plugging upper portions of the nano-scale openings with additional trench fill material, thereby defining porous STI regions in the substrate.

Abstract: Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

Abstract: A structure and method of forming a conducting via for connecting two back end of the line (BEOL) metal wiring levels is described. The method includes forming a first interconnect structure having a first dimensional width in a first dielectric layer; depositing a second dielectric layer over said first dielectric layer; etching an interconnect trench in the said second dielectric layer; etching a interconnect via using a photo resist mask to form a first portion of the transitional via; reacting the photo resist to expand the photo resist at least in the lateral direction; etching the said dielectric layer using the reacted photo resist to form the second portion of the transitional via; and filling the said interconnect trench and the said interconnect via with metal.

Abstract: A resist polymer that has nano-scale patterns located therein that are in the form of sub lithographic hollow pores (or openings) that are oriented in a direction that is substantially perpendicular with that of its major surfaces (top and bottom) is provided. Such a resist polymer having the nano-scale patterns is used as an etch mask transferring nano-scale patterns to an underlying substrate such as, for example, dielectric material. After the transferring of the nano-scale patterns into the substrate, nano-scale voids (or openings) having a width of less than 50 nm are created in the substrate. The presence of the nano-scale voids in a dielectric material lowers the dielectric constant, k, of the original dielectric material.

Abstract: A personal care composition comprising an alkylene oxide-lactone based polymer, the polymer comprising an alkylene oxide and a lactone in copolymerized form, is useful for treating hair and skin.

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: A method and a resist composition. The resist composition includes a polymer having repeating units having a lactone moiety, a thermal base generator capable of generating a base and a photosensitive acid generator. The polymer has the properties of being substantially soluble in a first solvent and becoming substantially insoluble after heating the polymer. The method includes forming a film of a photoresist including a polymer, a thermal base generator capable of releasing a base, a photosensitive acid generator, and a solvent. The film is patternwise imaged. The imaging includes exposing the film to radiation, resulting in producing an acid catalyst. The film is developed in an aqueous base, resulting in removing base-soluble regions and forming a patterned layer. The patterned layer is baked above the temperature, resulting in the thermal base generator releasing a base within the patterned layer and the patterned layer becoming insoluble in the solvent.

Abstract: A method and a resist composition. The resist composition includes a polymer having repeating units having a lactone moiety, a thermal base generator capable of generating a base and a photosensitive acid generator. The polymer has the properties of being substantially soluble in a first solvent and becoming substantially insoluble after heating the polymer. The method includes forming a film of a photoresist including a polymer, a thermal base generator capable of releasing a base, a photosensitive acid generator, and a solvent. The film is patternwise imaged. The imaging includes exposing the film to radiation, resulting in producing an acid catalyst. The film is developed in an aqueous base, resulting in removing base-soluble regions and forming a patterned layer. The patterned layer is baked above the temperature, resulting in the thermal base generator releasing a base within the patterned layer and the patterned layer becoming insoluble in the solvent.