Abstract: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract: A semiconductor structure includes a semiconductor device including a contact region. The semiconductor structure also includes a passivation layer passivating the semiconductor device including the contact region. A narrow bottomed stepped sidewall contact aperture is located within the passivation layer to expose the contact region. A corresponding narrow bottomed stepped sidewall contact via is located within the narrow bottomed stepped sidewall contact aperture to contact the contact region. The narrow bottomed stepped sidewall contact aperture and contact via provide for improved contact to the contact region and reduced parasitic capacitance with respect to the semiconductor device. Methods for fabricating the narrow bottomed stepped sidewall contact aperture use a mask layer (either dimensionally diminished or dimensionally augmented) in conjunction with a two step etch method.

Abstract: A resist polymer that has nano-scale patterns located therein that are in the form of sub lithographic hollow pores (or openings) that are oriented in a direction that is substantially perpendicular with that of its major surfaces (top and bottom) is provided. Such a resist polymer having the nano-scale patterns is used as an etch mask transferring nano-scale patterns to an underlying substrate such as, for example, dielectric material. After the transferring of the nano-scale patterns into the substrate, nano-scale voids (or openings) having a width of less than 50 nm are created in the substrate. The presence of the nano-scale voids in a dielectric material lowers the dielectric constant, k, of the original dielectric material.

Abstract: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

Abstract: A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.

Abstract: A method forms a blocking mask first and then patterns a contact hole mask over the blocking mask to provide a method of patterning contact holes in a substrate. This method first forms a blocking layer on the substrate and then patterns the blocking layer to have first openings to form the blocking mask. Next, the method forms the contact hole layer on the substrate and the blocking mask, and patterns the contact hole layer to have regularly spaced second openings to form the contact hole mask. The patterning of the contact hole layer does not affect the blocking mask and the contact hole mask is aligned directly over the blocking mask. Then, the substrate is patterned through the first openings and the second openings such that the substrate is patterned only where the first openings and the second openings align with each other. Thus, the blocking mask controls which of the regularly spaced second openings will transfer into the substrate.

Abstract: The present invention relates to a semiconductor device having first and second active device regions that are located in a semiconductor substrate and are isolated from each other by an isolation region therebetween, while the semiconductor device contains a first sub-lithographic interconnect structure having a width ranging from about 20 nm to about 40 nm for connecting the first active device region with the second active device region. The semiconductor device preferably contains at least one static random access memory (SRAM) cell located in the semiconductor substrate, and the first sub-lithographic interconnect structure directly cross-connects a pull-down transistor of the SRAM cell with a pull-up transistor thereof without any metal contact therebetween. The first sub-lithographic interconnect structure can be readily formed by lithographic patterning of a mask layer, followed by formation of sub-lithographic features using either self-assembling block copolymers or dielectric sidewall spacers.

Abstract: A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility in pFET devices. UV exposure of this compressive, low k material results in changing the polarity of the low k stress liner from compressive to tensile. The use of such a tensile, low k stress liner improves electron mobility in nFET devices.

Abstract: A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench insulation (STI) regions adjacent to the nFETs and pFETs thus can be formed to induce different stress to the channel regions of the respective nFETs and pFETs. As a consequence, performance of both the nFETs and the pFETs can be improved by the STI stress. In addition, the area of the IC can also be reduced as the two silicon layers are positioned vertically relative to one another.

Abstract: A method in which during the formation of damascene features in a semiconductor structure, a planarization material is added to vias formed in the dielectric to protect the vias during subsequent lithographic processing. The planarization material preferred is a developable photosensitive material which can be exposed and developed to define the damascene features rather than etching as is conventional.

Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) devices having a continuous dielectric stressor layer containing regions of opposite stresses. Specifically, each CMOS device of the present invention includes at least one n-channel field effect transistor (n-FET) and at least one p-channel field effect transistor (p-FET). A continuous dielectric stressor layer, which overlays both the at least one n-FET and the at least one p-FET, contains a first, tensilely stressed region that selectively overlays the at least one n-FET and a second, compressively stressed region that selectively overlays the at least one p-FET. Such a continuous dielectric stressor layer can be readily formed by first depositing a continuous, compressively stressed dielectric layer and then converting a selected region of such a layer from being compressively stressed to being tensilely stressed by ultraviolet (UV) exposure.

Abstract: A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w<d. Each single unit polymer block of the present invention is embedded in a polymeric matrix and can be selectively removed against the polymeric matrix to form a single opening of the diameter w in the polymeric matrix inside each of the mask openings. Sub-lithography feature patterning can then be conducted in the device structure using the single openings of diameter w.

Abstract: Disclosed are embodiments of a bi-layer bottom anti-reflective coating (BARC) with graded optical properties (i.e., a graded refractive index) and a method of forming the BARC. The BARC is formed by sequentially coating two BARC layers onto a substrate. Each BARC layer comprises a polymer and an optical component, each has slightly different optical properties, and each is processed such that either the polymers partially intermix or the optical component partially diffuses between the layers in order to create a graded chromophore concentration across the resulting BARC. Thus, a gradual transition of optical properties is created from the substrate/BARC interface to the BARC/photo-resist interface.

Abstract: A film stack is provided in which a first film including a first polymer directly contacts a surface of a substrate at which a given material is exposed. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface contacting the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

Abstract: A method is provided for forming a film stack in which a first film including a first polymer is formed on a substrate. A second film, which can include a second polymer other than the first polymer, is formed to have an inner surface disposed on the first film. The second film can have a thickness at which a free energy of the second film would be negative if the second film were disposed directly on the substrate. Desirably, the resulting second film is substantially free of dewetting defects.

Abstract: A film stack and method of forming a film stack are provided in which a first film is disposed on a substrate and a second film has an inner surface disposed on the first film. The second film has a thickness smaller than a reference thickness at which the second film would begin to dewet from the substrate if the second film were disposed directly on the substrate. However, the second film is substantially free of dewetting defects because it is disposed overlying the first film which has a first Hamaker constant having a negative value with respect to the substrate.

Abstract: A method of forming a relief image on a substrate including: applying over a substrate a layer of an antireflective coating; and vacuum processing the antireflective coating. This method reduces the number of pinhole defects present in the antireflective coating.

Abstract: The present invention is directed to systems and methods for radiating radar signals, communication signals, or other similar signals. In one embodiment, a system includes a controller that generates a control signal and an antenna coupled to the controller. The antenna includes a first component that generates at least one wave based on the generated control signal and a metamaterial lens positioned at some predefined focal length from the first component. The metamaterial lens directs the generated at least one wave.

Abstract: A method of forming a thin film is provided in which a film having a first thickness is deposited over a substrate, wherein the first thickness is greater than a thickness at which the initially deposited film begins to dewet from the substrate. The initially deposited film is then stabilized to form a stabilized film. Thereafter, the stabilized film is then thinned to a second thickness, such that the resulting film now has a smaller thickness than the thickness at which the initially deposited film would begin to dewet from the substrate. However, as a result of the prior stabilization, the reduced thickness film remains free of dewetting defects.