Abstract: A lighting device is provided. The lighting device includes a substrate, integrated circuits (22?, 24), embedded passive components (26, 27), and a lighting component (22), the device being arranged in an architecture having three layers: an integrated circuits layer (11) including the integrated circuits (22?, 24), wherein the integrated circuits layer (11) is integrated on a first side of the substrate; an embedded passive components layer (12) including the embedded passive components (26, 27), wherein the embedded passive components (26, 27) are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits (22?, 24) through vias (28) in the substrate; and a bonded layer (13), including the lighting component (22), the lighting component (22) being connected to the integrated circuit layer (11) through flip-chip bonding or monolithic integration.

Abstract: The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel.

Abstract: The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Abstract: In certain aspects of the invention, an isolator is configured by a reception circuit, a transmission circuit, and a transformer. In some aspects, the transmission circuit is disposed in an anterior surface of a semiconductor substrate. The transformer is disposed in a posterior surface of the semiconductor substrate and transmits in an electrically isolated state to the reception circuit, a signal input from the transmission circuit. The transformer is configured by a primary coil and a secondary coil. The primary coil can be configured by a metal film embedded in an oxide film inside a coil trench. The secondary coil can be disposed inside an insulating film covering the primary coil so as to oppose the primary coil and is insulated from the primary coil by the insulating film.

Abstract: A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a semi-insulating field plate interconnecting said first and second metal electrodes, and an insulating oxide layer extending between said first and second metal electrodes and between said field plate and said semiconductor substrate, wherein said semi-insulating field plate is a titanium nitride (TiN) field plate.

Abstract: Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

Abstract: A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.

Abstract: The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel.

Abstract: The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source (14) of a first conductivity type, a doped body (15) of a second conductivity type, a source electrode (20) short-connecting the doped body and the doped source, a doped drift region (10) of the first conductivity type, a first layer (30) of a gate dielectric region (36) covering the surface of the doped drift region (10), and forming channel from the doped source (14) to the doped drift region (10), a second layer (31) of the gate dielectric region (36) over the first layer (30), a third layer (32) of the gate dielectric region (36) over the second layer (31), and a gate electrode (21) over the third layer (32).

Abstract: Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.

Abstract: The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source (14) of a first conductivity type, a doped body (15) of a second conductivity type, a source electrode (20) short-connecting the doped body and the doped source, a doped drift region (10) of the first conductivity type, a first layer (30) of a gate dielectric region (36) covering the surface of the doped drift region (10), and forming channel from the doped source (14) to the doped drift region (10), a second layer (31) of the gate dielectric region (36) over the first layer (30), a third layer (32) of the gate dielectric region (36) over the second layer (31), and a gate electrode (21) over the third layer (32).

Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

Abstract: Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.

Abstract: Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

Abstract: A MOSFET comprising an epitaxial layer of a semiconductor substrate of a first conductivity type, the MOSFET comprises a polysilicon gate, a source region of the first conductivity type and a body region of a second conductivity type, the polysilicon gate comprises a first layer of polysilicon and a second layer of polysilicon sandwiching a layer of polysilicon etch stop substances.

Abstract: This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step.

Abstract: Current practice of the common source configuration is to connect the sources of the two discrete MOSFETs (housed either in separated packages or in a single package) externally on the printed circuit board. Because the gate pads and source pads of the two dies are alternatively placed between gate and source, it does not allow the sources of the power MOSFETs to be connected internally, which requires an additional layer of circuit board to connect the sources and the gates externally. This invention provides a novel electronic device layout design and a novel packaging technique for common source configuration, placing two MOSFETs in a package with their sources connected to a single source post which is located between tow gate posts. In order to facilitate gate bonding and to prevent any shorting between gate and source, two gate pads are used and placed at the upper adjacent corners of each MOSFET.

Abstract: A method of forming a power MOSFET having a substrate of a first conductivity type and a body region of a second conductivity type. The method includes the steps of forming a gate region of a predetermined pattern and with a plurality of gate elements partially covering the substrate. The gate element has a stepped cross-sectional profile with a thicker portion and a thinner portion. The thicker portion is adapted to substantially prevent passage of impurities therethrough into the substrate during the impurities implantation step. The thinner portion is adapted to allow partial passage of impurities therethrough during the impurities implantation step. Impurities are implanted into the substrate from the gate region side of the substrate to form a body region of the second conductivity type.

Abstract: This invention describes a process for making a high density trench DMOS (Double-diffused Metal Oxide Semiconductor) transistor with improved gate oxide breakdown at the three-dimensional trench corners and better body contact which can improve the latch-up immunity and increase the drive current. A guard-ring mask is used to define a deep body to cover the three-dimensional trench corners, which can prevent early gate-oxide breakdown during the off-state operation. Another function of the guard-ring mask is to define self-aligned deeper trenches at the terminations of the trenches. The deeper trenches at the terminations of the trenches will result in thicker gate oxide grown at the terminations. This layer of thicker oxide is used to prevent the pre-mature gate oxide breakdown at the three-dimensional trench corners. A trench spacer is formed after the N-body drive-in step by depositing a layer of oxide and then followed by an oxide etch-back step.

Abstract: The present invention provides a novel thin film transistor device having the advantages of both conventional thin and thick film devices. The channel region of the device is elevated with respect to the source and drain regions by being made as a thin film while the source and drain regions are relatively thick. Such an arrangement provides high drive current characteristics of a thin film device, whilst mitigating the disadvantageous kink effect in the IV curve and the off-state leakage current known in conventional thin film devices. The invention also provides a fabrication method, and this method may also be employed to manufacture other novel semiconductor devices including EEPROM devices, large double layer storage capacitors and a novel conductivity modulated thin film transistor.