Patents by Inventor King Ho Tam
King Ho Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170116361Abstract: In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.Type: ApplicationFiled: January 6, 2017Publication date: April 27, 2017Inventors: KING-HO TAM, YEN-PIN CHEN, WEN-HAO CHEN, CHUNG-HSING WANG
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Publication number: 20170039310Abstract: A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Inventors: Chung-Hsing WANG, King-Ho TAM, Yen-Pin CHEN, Wen-Hao CHEN, Chung-Kai LIN, Chih-Hsiang YAO
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Patent number: 9563734Abstract: In some embodiments, in a method performed by at least one processor, a cell is characterized, by the at least one processor, with respect to an input transition characteristic considering different circuit topologies of a pre-driver driving the cell resulting in the same input transition characteristic.Type: GrantFiled: January 8, 2014Date of Patent: February 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Hsing Wang
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Patent number: 9509301Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.Type: GrantFiled: June 28, 2013Date of Patent: November 29, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jerry Chang-Jui Kao, Chien-Ju Chao, Chou-Kun Lin, Chin-Shen Lin, King-Ho Tam, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9477803Abstract: A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.Type: GrantFiled: July 30, 2014Date of Patent: October 25, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Hsing Wang, King-Ho Tam, Yen-Pin Chen, Wen-Hao Chen, Chung-Kai Lin, Chih-Hsiang Yao
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Publication number: 20160239599Abstract: In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: CHUNG-HSING WANG, KING-HO TAM, YUAN-TE HOU, CHIN-CHANG HSU, MENG-KAI HSU
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Patent number: 9400866Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: GrantFiled: August 24, 2015Date of Patent: July 26, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang
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Patent number: 9311440Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.Type: GrantFiled: May 10, 2012Date of Patent: April 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jerry Kao, King-Ho Tam, Meng-Xiang Lee, Li-Chung Hsu, Chi-Yeh Yu, Chung-Min Fu, Chung-Hsing Wang
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Publication number: 20160034631Abstract: A method of generating a techfile corresponding to a predetermined fabrication process is disclosed. The method includes determining a typical value and a corner variation value usable to model an electrical characteristic of a layer of back end of line (BEOL) features to be fabricated by the predetermined fabrication process, based on measurement of one or more sample integrated circuit chips fabricated by the predetermined fabrication process. A reduced variation value is calculated based on the corner variation value and a scaling factor. The techfile is generated based on the typical value and the reduced variation value.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Chung-Hsing WANG, King-Ho TAM, Yen-Pin CHEN, Wen-Hao CHEN, Chung-Kai LIN, Chih-Hsiang YAO
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Publication number: 20150363540Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Xiang LEE, Li-Chung HSU, Shih-Hsien YANG, Ho Che YU, King-Ho TAM, Chung-Hsing WANG
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Patent number: 9201107Abstract: A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor.Type: GrantFiled: October 21, 2013Date of Patent: December 1, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Nitesh Katta, Jerry Chang-Jui Kao, King-Ho Tam, Kuo-Nan Yang, Chung-Hsing Wang
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Patent number: 9129078Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.Type: GrantFiled: October 30, 2013Date of Patent: September 8, 2015Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Patent number: 9122839Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: GrantFiled: August 1, 2014Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang
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Publication number: 20150193569Abstract: In some embodiments, in a method performed by at least one processor, a cell is characterized, by the at least one processor, with respect to an input transition characteristic considering different circuit topologies of a pre-driver driving the cell resulting in the same input transition characteristic.Type: ApplicationFiled: January 8, 2014Publication date: July 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: KING-HO TAM, YEN-PIN CHEN, WEN-HAO CHEN, CHUNG-HSING WANG
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Patent number: 9058462Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.Type: GrantFiled: August 30, 2013Date of Patent: June 16, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: King-Ho Tam, Yeh-Chi Chang, Kuo-Nan Yang, Zhe-Wei Jiang, Chung-Hsing Wang
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Publication number: 20150067624Abstract: A system and method of producing an integrated circuit using abutted cells having shared polycrystalline silicon on an oxide definition region edge (PODE) includes modeling inter-cell leakage current in a plurality of different cells. Each of the plurality of different cells is abutted with another cell and having the shared PODE. The method also comprises verifying a pre-determined acceptable power consumption of the integrated circuit based on the inter-cell leakage current.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: King-Ho TAM, Yeh-Chi CHANG, Kuo-Nan YANG, Zhe-Wei JIANG, Chung-Hsing WANG
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Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
Patent number: 8966421Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: September 10, 2013Date of Patent: February 24, 2015Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam -
Publication number: 20150035551Abstract: A method for cell characterization with Miller capacitance includes characterizing input capacitance of an input of a first stage in a cell by considering a first current transition at the input of the first stage up to a first stop time. The first stop time occurs during the first current transition exhibits a substantial tail portion contributed by the later of a first input voltage transition and a first output voltage transition reaching a corresponding steady state voltage. The first input voltage transition is associated with the input of the first stage. The first output voltage transition is associated with an output of the first stage coupled to the input through a capacitor.Type: ApplicationFiled: October 21, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: NITESH KATTA, JERRY CHANG-JUI KAO, KING-HO TAM, KUO-NAN YANG, CHUNG-HSING WANG
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Publication number: 20150001934Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Jerry Chang-Jui KAO, Chien-Ju CHAO, Chou-Kun LIN, Chin-Shen LIN, King-Ho TAM, Kuo-Nan YANG, Chung-Hsing WANG
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Publication number: 20140351784Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: ApplicationFiled: August 1, 2014Publication date: November 27, 2014Inventors: Meng-Xiang LEE, Li-Chung HSU, Shih-Hsien YANG, Ho Che YU, King-Ho TAM, Chung-Hsing WANG