Patents by Inventor King Ho Tam
King Ho Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8826195Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: GrantFiled: June 22, 2012Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Meng-Xiang Lee, Li-Chung Hsu, Shih-Hsien Yang, Ho Che Yu, King-Ho Tam, Chung-Hsing Wang
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Patent number: 8826212Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.Type: GrantFiled: March 11, 2013Date of Patent: September 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yen Yeh, Yeh-Chi Chang, Yen-Pin Chen, Zhe-Wei Jiang, King-Ho Tam, Yuan-Te Hou, Chung-Hsing Wang
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Patent number: 8694945Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.Type: GrantFiled: December 20, 2011Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsing Wang, King-Ho Tam, Huang-Yu Chen
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Patent number: 8615725Abstract: Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.Type: GrantFiled: June 5, 2012Date of Patent: December 24, 2013Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, King Ho Tam
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Publication number: 20130326438Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.Type: ApplicationFiled: June 22, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Xiang LEE, Li-Chung HSU, Shih-Hsien YANG, Ho Che YU, King-Ho TAM, Chung-Hsing WANG
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Patent number: 8595669Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design may be partitioned into a plurality of circuit stages. A timing graph including timing arcs is constructed to represent the timing delays in circuit stages of the integrated circuit design. A model of each circuit stage may be formed including a model of a victim driver, an aggressor driver, a victim receiver, and a victim net and an aggressor net coupled together. For each timing arc in the timing graph, full timing delays may be computed for the timing arcs in each circuit stage.Type: GrantFiled: September 2, 2008Date of Patent: November 26, 2013Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Publication number: 20130304449Abstract: A method includes identifying at least one local power segment of a circuit, estimating at least one performance parameter of the at least one power segment based on a computer-based simulation of the circuit, and changing a design of the circuit based on at least one electromigration avoidance strategy if the at least one parameter is greater than or equal to a threshold value. A data file representing the circuit is stored if the at least one parameter is less than the threshold value.Type: ApplicationFiled: May 10, 2012Publication date: November 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jerry KAO, King-Ho TAM, Meng-Xiang LEE, Li-Chung HSU, Chi-Yeh YU, Chung-Min FU, Chung-Hsing WANG
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Patent number: 8543954Abstract: Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.Type: GrantFiled: September 2, 2008Date of Patent: September 24, 2013Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vinod Kariat, King Ho Tam
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Patent number: 8533644Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: December 12, 2010Date of Patent: September 10, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam
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Patent number: 8516420Abstract: In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.Type: GrantFiled: August 31, 2007Date of Patent: August 20, 2013Assignee: Cadence Design Systems, Inc.Inventors: Vinod Kariat, Igor Keller, Joel R. Phillips, King Ho Tam
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Patent number: 8499274Abstract: A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.Type: GrantFiled: February 23, 2012Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Ju Chao, Jerry Chang-Jui Kao, King-Ho Tam, Chung-Hsing Wang, Huan Chi Tseng
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Publication number: 20130154128Abstract: The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and route tool constructs a local power network having multi-level power rails. The multi-level power rails have interleaved segments of vertically adjacent metal layers, wherein each interleaved segment is shorter than a predetermined characteristic length corresponding to a Blech length. By limiting the length of the interleaved metallization segments, electromigration within the multi-level power rails is alleviated, allowing for the maximum current density requirement (Jmax) for mean time to failures (MTTF) to be increased.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Hsing Wang, King-Ho Tam, Huang-Yu Chen
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Publication number: 20130139120Abstract: A tool includes one or more machine readable storage mediums encoded with data. The data include a list of standard cells included in an integrated circuit (IC) design The data include a nominal leakage value approximating a respective median leakage value for each of the plurality of standard cells at a predetermined temperature and voltage. The data include at least one table including adjustment factors for calculating leakage based on voltage, temperature and process variations. The table includes a respective statistical scaling factor, for computing a mean leakage corresponding to a given median leakage. A processor is programmed to calculate and output a total IC leakage for the IC design at an input voltage and input temperature, based on the list, the nominal leakage values, the input voltage, the input temperature and at least one of the adjustment factors.Type: ApplicationFiled: February 23, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Ju Chao, Jerry Chang-Jui Kao, King-Ho Tam, Chung-Hsing Wang, Huan Chi Tseng
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Patent number: 8302046Abstract: Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.Type: GrantFiled: November 11, 2008Date of Patent: October 30, 2012Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, King Ho Tam