Patents by Inventor King Owyang
King Owyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10032901Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: April 5, 2016Date of Patent: July 24, 2018Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20170025527Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: April 5, 2016Publication date: January 26, 2017Inventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Patent number: 9306056Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: October 30, 2009Date of Patent: April 5, 2016Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20150331438Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 9093359Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: July 28, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 9040356Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: GrantFiled: June 19, 2009Date of Patent: May 26, 2015Assignee: Vishay-SiliconixInventors: Mike Chang, King Owyang, Yueh-Se Ho, Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 8928138Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: May 13, 2010Date of Patent: January 6, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8471381Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: June 25, 2013Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8269263Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.Type: GrantFiled: May 12, 2008Date of Patent: September 18, 2012Assignee: Vishay-SiliconixInventors: Jian Li, King Owyang
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Publication number: 20110101525Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: VISHAY-SILICONIXInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20100219519Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20090278176Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.Type: ApplicationFiled: May 12, 2008Publication date: November 12, 2009Applicant: VISHAY-SILICONIXInventors: Jian Li, King Owyang
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Publication number: 20090256246Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: ApplicationFiled: June 19, 2009Publication date: October 15, 2009Applicant: VISHAY-SILICONIXInventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 7595547Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: GrantFiled: June 13, 2005Date of Patent: September 29, 2009Assignee: Vishay-SiliconixInventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 7394150Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: GrantFiled: November 23, 2004Date of Patent: July 1, 2008Assignee: Siliconix incorporatedInventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Patent number: 7326995Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide.Type: GrantFiled: June 22, 2005Date of Patent: February 5, 2008Assignee: Siliconix incorporatedInventors: Mohamed N. Darwish, King Owyang
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Patent number: 7238551Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: GrantFiled: November 23, 2004Date of Patent: July 3, 2007Assignee: Siliconix incorporatedInventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen
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Publication number: 20070063341Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: June 30, 2006Publication date: March 22, 2007Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20070063340Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: June 30, 2006Publication date: March 22, 2007Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20060110856Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: ApplicationFiled: November 23, 2004Publication date: May 25, 2006Inventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen