Abstract: A header region evaluation circuit includes a difference signal detection unit that detects a difference signal proportional to a difference in amounts of received light from an optical disc, a high pass filter that switches a plurality of cutoff frequencies according to a passband control signal, removes a low frequency component from the difference signal, and generates a difference signal HPF output, a waveform shaping unit that generates a shaping signal to convert the difference signal HPF output into a pulse, and a physical header detection sequencer that generates a groove detection signal for evaluating whether the physical header region is either one of a groove and an inter-groove and generates a passband control signal for controlling the cutoff frequency to be reduced for a difference signal corresponding to at least a part of the physical header region.

Abstract: A header region evaluation circuit includes a difference signal detection unit that detects a difference signal proportional to a difference in amounts of received light from an optical disc, a high pass filter that switches a plurality of cutoff frequencies according to a passband control signal, removes a low frequency component from the difference signal, and generates a difference signal HPF output, a waveform shaping unit that generates a shaping signal to convert the difference signal HPF output into a pulse, and a physical header detection sequencer that generates a groove detection signal for evaluating whether the physical header region is either one of a groove and an inter-groove and generates a passband control signal for controlling the cutoff frequency to be reduced for a difference signal corresponding to at least a part of the physical header region.

Abstract: A wobble signal extracting circuit includes: a readout signal generating circuit generating an RF signal by adding first and second detection signals corresponding to reflected light from inside and outside a recording track; a first subtractor generating a push-pull signal by subtracting the first and second detection signals, respectively; a first analog-to-digital converter (ADC) converting the RF signal to digital; a second ADC converting the push-pull signal to digital; a residual RF component generating circuit generating a residual RF signal component equivalent to the RF signal component remaining in the digitized push-pull signal; and a second subtractor generating the wobble signal by subtracting the residual RF signal component from the digitized push-pull signal. The residual RF component generating circuit generates the residual RF signal component so that it may approach the remaining RF signal component based on correlation between the wobble signal and the digitized RF signal.

Abstract: A wobble signal extracting circuit includes: a readout signal generating circuit generating an RF signal by adding first and second detection signals corresponding to reflected light from inside and outside a recording track; a first subtractor generating a push-pull signal by subtracting the first and second detection signals, respectively; a first analog-to-digital converter (ADC) converting the RF signal to digital; a second ADC converting the push-pull signal to digital; a residual RF component generating circuit generating a residual RF signal component equivalent to the RF signal component remaining in the digitized push-pull signal; and a second subtractor generating the wobble signal by subtracting the residual RF signal component from the digitized push-pull signal. The residual RF component generating circuit generates the residual RF signal component so that it may approach the remaining RF signal component based on correlation between the wobble signal and the digitized RF signal.

Abstract: A small size circuit reproducing data with low error rate even when a signal includes a non-linear distortion is desired. In such a circuit, the Viterbi method is performed. In the Viterbi method, branch metrics are calculated based on a difference of a sampled reproduction signal and a predetermined expectation values. Path metrics are calculated from the branch metrics. Paths among the plurality of paths having the calculated path metrics and merging at a same state are compared with one another. Based on the magnitude of the compared path metrics, survivor path is selected. In the circuit, for the path metrics of paths merging at a same state, offset corresponding to a determination result until a merging point is added to the paths for the comparison for determining the survivor path from the plurality of merging paths.

Abstract: A small size circuit reproducing data with low error rate even when a signal includes a non-linear distortion is desired. In such a circuit, the Viterbi method is performed. In the Viterbi method, branch metrics are calculated based on a difference of a sampled reproduction signal and a predetermined expectation values. Path metrics are calculated from the branch metrics. Paths among the plurality of paths having the calculated path metrics and merging at a same state are compared with one another. Based on the magnitude of the compared path metrics, survivor path is selected. In the circuit, for the path metrics of paths merging at a same state, offset corresponding to a determination result until a merging point is added to the paths for the comparison for determining the survivor path from the plurality of merging paths.

Abstract: The invention device has amplitude correction means for generating, from a radial push-pull signal, a wobble signal which has been corrected such that the amplitude of a predetermined frequency component is kept substantially constant, and for outputting a magnification for correcting the amplitude of the predetermined frequency component as a gain control signal, and determination means for determining whether or not wobble exists based on a minimum value of the magnification indicated by the gain control signal.

Abstract: The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.

Abstract: In a method of and an apparatus for creating a reproduced wobble signal by subtracting an estimated crosstalk signal, expressed by a sine waveform having a frequency approximately equal to the meandering frequency of grooves, from an original wobble signal and recording or reproducing an information pattern at a predetermined position of an optical disc, a carrier signal, which is caused to correspond to the meandering of the groove by being subjected to phase synchronization, is assumed based on the reproduced wobble signal, a crosstalk remaining component is estimated from the amplitude and phase of the region, which meanders in approximately the same phase as the estimated carrier signal in the reproduced wobble signal, and from the amplitude and phase of the region which meanders according to a signal different from the estimated carrier signal, and the estimated crosstalk is updated to cancel the remaining component.

Abstract: A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

Abstract: In a method of and an apparatus for creating a reproduced wobble signal by subtracting an estimated crosstalk signal, expressed by a sine waveform having a frequency approximately equal to the meandering frequency of grooves, from an original wobble signal and recording or reproducing an information pattern at a predetermined position of an optical disc, a carrier signal, which is caused to correspond to the meandering of the groove by being subjected to phase synchronization, is assumed based on the reproduced wobble signal, a crosstalk remaining component is estimated from the amplitude and phase of the region, which meanders in approximately the same phase as the estimated carrier signal in the reproduced wobble signal, and from the amplitude and phase of the region which meanders according to a signal different from the estimated carrier signal, and the estimated crosstalk is updated to cancel the remaining component.

Abstract: The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.

Abstract: The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.

Abstract: A data bit stream is segmented into 4-bit data words and successively shifted two bits at a time. For each 4-bit data word a corresponding 3-bit code word is detected in a conversion table. Two higher significant bits of each data word is converted to the detected code word and two lower significant bits of the data word is then converted as two higher significant bits of a subsequent data word to a corresponding code word, so that a channel bit stream formed by a series of such code words has no consecutive 1's. A digital sum value of the channel bit stream is determined and a search is made for a code word “010” which is consecutive with a code word “000”. The detected code word “010” is replaced with a substitute code word “000” if the replacement results in the digital sum value approaching zero.

Abstract: A recording data string is composed of a plurality of synchronous frames each of which has synchronous data and coding data. Data items in the coding data contributed to creation of the same column of the error correction code are arranged at regular intervals of E in the recording data string. A data segment length L is obtained by adding an additional synchronous frame to the recording data string. Wherein, a physical segment length A satisfies the equation L=mA, m is a natural number. And A is set indivisible by E.

Abstract: A VCO, which good temperature characteristics, high frequency accuracy, and high phase accuracy is provided as an LSI, without making its master clock frequency operate the VCO high. The VCO includes a digital VCO, a phase modulator, and a frequency band limiting element. The digital VCO outputs an oscillating frequency clock and a phase difference lower than an output cycle resolution at the same timing as the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from positions near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference.

Abstract: An optical disk includes grooves (G) formed concentrically or spirally from an inner periphery to an output periphery of a disk, wherein prepit (1) are formed on the lands (L) each sandwiched between grooves and grooves (G). The prepit forming region (2) is assigned as a region in which a single or a plurality of prepits (1) are formed. Th prepit forming regions (2) have a fixed length 36 or less times the recording channel length along the recording track, and are arranged apart from on another by 300 or more times the recording channel bit length along the recording track. On the prepit forming region (2), a pattern including a long mark or a long space having a length ten or more times the recording channel bit length so that the long mark or long space covers the prepit (1) on the recording track.

Abstract: A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ? which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal. A frequency component of the signal is reduced from a maximum value of the frequency component by 20 dB or less as a power density at a frequency of {fraction (1/10,000)} or less of a channel clock frequency.

Abstract: A recording data string is composed of a plurality of synchronous frames each of which has synchronous data and coding data. Data items in the coding data contributed to creation of the same column of the error correction code are arranged at regular intervals of E in the recording data string. A data segment length L is obtained by adding an additional synchronous frame to the recording data string. Wherein, a physical segment length A satisfies the equation L=mA, m is a natural number. And A is set indivisible by E.