Abstract: The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ⅔ which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal.

Abstract: A data bit stream is segmented into 4-bit data words and successively shifted two bits at a time. For each 4-bit data word a corresponding 3-bit code word is detected in a conversion table. Two higher significant bits of each data word is converted to the detected code word and two lower significant bits of the data word is then converted as two higher significant bits of a subsequent data word to a corresponding code word, so that a channel bit stream formed by a series of such code words has no consecutive 1's. A digital sum value of the channel bit stream is determined and a search is made for a code word “010” which is consecutive with a code word “000”. The detected code word “010” is replaced with a substitute code word “000”if the replacement results in the digital sum value approaching zero.

Abstract: A VCO, in which its temperature characteristics are good and its high frequency accuracy and high phase accuracy can be realized without making its master clock frequency to operate the VCO high and its circuit can be realized as an LSI, is provided. Further, a PLL circuit using this VCO and a data recording apparatus using this PLL circuit are provided. The VCO provides a digital VCO, a phase modulator, and a frequency band limiting means. The digital VCO outputs an oscillating frequency clock and phase difference being lower than output cycle resolution at the same timing of the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from the position near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference. The frequency band limiting means such as a BPF eliminates the side-band components moved to the farther bands.

Abstract: A method of replacement processing for secondary defects is provided that can maintain both the transfer rate and quality of write/read data at high levels. According to the method, a change-permitted range in which changes in the assignment of logical addresses is allowed is acquired, and when sectors having secondary defects due to write abnormalities are detected, replacement of sectors is carried out as long as changes in the assignment of logical addresses do not go beyond sectors in the change-permitted range by: omitting the secondary defect sectors by additionally registering the defective sectors in a slip replacement list, and shifting back the assignment of logical addresses as long as there are free sectors following the abnormal sectors.

Abstract: An equalizer is controlled to equalize a signal read from an optical disc. The equalized signal is supplied to a maximum-likelihood sequence detection circuit, in which a signal sequence is detected to be most coincident to the equalized signal among signal sequences meeting a state transition regularity. The equalizer operates for equalization, only when an error signal is detected in the vicinity of the end of a region having a code transition interval of more than number of minimum transition interval.