Patents by Inventor Kinya Goto
Kinya Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9368459Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: December 23, 2014Date of Patent: June 14, 2016Assignee: ACACIA RESEARCH GROUP LLCInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20150108613Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Applicant: Renesas Electronics CorporationInventors: Takeshi FURUSAWA, Noriko MIURA, Kinya GOTO, Masazumi MATSUURA
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Patent number: 8963291Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: May 20, 2011Date of Patent: February 24, 2015Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 8390135Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.Type: GrantFiled: May 18, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Yoshihiro Oka, Kinya Goto
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Publication number: 20110298133Abstract: The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings.Type: ApplicationFiled: May 18, 2011Publication date: December 8, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro OKA, Kinya GOTO
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Patent number: 8018030Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: March 24, 2009Date of Patent: September 13, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20110215447Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: May 20, 2011Publication date: September 8, 2011Applicant: Renesas Electronics CorporationInventors: Takeshi Furusawa, Norio Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7981790Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: GrantFiled: January 7, 2010Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7960279Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: GrantFiled: June 29, 2009Date of Patent: June 14, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20100112805Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Patent number: 7671473Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: GrantFiled: June 14, 2006Date of Patent: March 2, 2010Assignee: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Publication number: 20090263963Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Applicant: Renesas Technology Corp.Inventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7605448Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: GrantFiled: September 8, 2005Date of Patent: October 20, 2009Assignee: Renesas Technology Corp.Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Patent number: 7602063Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.Type: GrantFiled: July 5, 2005Date of Patent: October 13, 2009Assignee: Renesas Technology Corp.Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20090189245Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.Type: ApplicationFiled: March 24, 2009Publication date: July 30, 2009Applicant: Renesas Technology CorporationInventors: Takeshi FURUSAWA, Noriko Miura, Kinya Goto, Masazumi Matsuura
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Publication number: 20080093709Abstract: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After that, UV cure is performed by introducing a small amount of an oxygen gas adjusted to an atmospheric pressure or a little more positive pressure in the chamber by nitrogen purge. For the introduction of an oxygen gas, an oxygen gas is introduced while controlling the flow rate by using a flow meter, and adjustment is performed using the flow meter so that the oxygen concentration in the chamber becomes a constant value in the range of 5 ppm to 400 ppm.Type: ApplicationFiled: October 19, 2007Publication date: April 24, 2008Inventors: Masazumi Matsuura, Kinya Goto, Hisashi Yano, Kotaro Nomura
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Publication number: 20070114668Abstract: A semiconductor device is equipped with a semiconductor chip which has at least one layer of first insulating film formed on a substrate, and a plurality of pads arranged on a layer higher than the first insulating film. The plurality of pads on the semiconductor chip are arranged parallel to a predetermined chip edge of the semiconductor chip. The first insulating film has a reinforcement pattern in a region underneath each of the plurality of pads. In the region underneath each pad, occupancy of the reinforcement pattern in the first insulating film is within a predetermined range permitted for the region underneath each pad and occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction perpendicular to the predetermined chip edge is higher than occupancy of the reinforcement pattern in a whole area of a row where the reinforcement pattern is arranged in a line in a direction parallel to the chip edge.Type: ApplicationFiled: November 20, 2006Publication date: May 24, 2007Applicant: Renesas Technology Corp.Inventors: Kinya Goto, Takeshi Furusawa, Masazumi Matsuura, Noriko Miura
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Patent number: 7208408Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.Type: GrantFiled: June 24, 2005Date of Patent: April 24, 2007Assignees: Matsushita Electric Industrial Co., Ltd., Mitsubishi Denki Kabushiki KaishaInventors: Hiroshi Yuasa, Tetsuo Satake, Masazumi Matsuura, Kinya Goto
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Publication number: 20060286814Abstract: There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer.Type: ApplicationFiled: June 14, 2006Publication date: December 21, 2006Applicant: Renesas Technology Corp.Inventors: Teruhiko Kumada, Hideharu Nobutoki, Naoki Yasuda, Kinya Goto, Masazumi Matsuura
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Publication number: 20060175705Abstract: A semiconductor device has a first insulating film formed on a substrate and having a first trenched portion, a second insulating film formed on the first insulating film, a third insulating film formed on the second insulating film and having a specific dielectric constant of 3 or less, and a first interconnection formed in the first trenched portion. The second insulating film is made of a compound containing silicon, oxygen, carbon, and nitrogen and the composition ratio of oxygen to silicon in the upper surface of the second insulating film is higher by 5% or more than in the bottom surface of the second insulating film.Type: ApplicationFiled: February 1, 2006Publication date: August 10, 2006Inventors: Makoto Tsutsue, Kinya Goto