Abstract: A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

Abstract: In a semiconductor having a multilayer wiring structure device on a semiconductor substrate, the multilayer wiring structure includes an interlayer insulating film having at least an organic siloxane insulating film. The organic siloxane insulating film has a relative dielectric constant of 3.1 or less, a hardness of 2.7 GPa or more, and a ratio of carbon atoms to silicon atoms between 0.5 and 1.0, inclusive. Further, the multilayer wiring structure may include an insulating layer having a ratio of carbon atoms to silicon atoms not greater than 0.1, the insulating layer being formed on the top surface of the organic siloxane insulating film as a result of carbon leaving the organic siloxane insulating film.

Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.

Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.

Abstract: A second-level wire is formed by a dual damascene process in a insulating film. In an upper surface of the first insulating film a metal film is formed and serves as a first electrode of an MIM-type capacitor. A second insulating films has a structure in which a plurality of insulating films are layered on a second interconnection layer, in this order. In a first insulating film of the plurality of insulating films, a second electrode of the MIM-type capacitor is formed. The second electrode has a first metal film formed on a second insulating film of the plurality of the insulating films and a second metal film is formed on the first metal film. A portion of the second insulating film which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor.

Abstract: A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusion prevention film may be prepared from a silicon oxynitride film or a silicon oxide film containing Si—H bonds. A spacer film is formed on a surface of the F diffusion prevention film and its surface is flattened. A second layer metal wire is formed on a surface of the spacer film. Thus implemented is a semiconductor device comprising an F diffusion prevention film preventing F atoms contained in an SiOF film from diffusing into an upper metal wire with the F diffusion prevention film not etched in formation of the upper metal wire and a method of manufacturing a semiconductor device not directly polishing an SiOF film by CMP.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 Hm over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: In an insulating film (I2), a second-level wire (W2) is formed by a dual damascene process. In an upper surface of the insulating film (I2) formed is a metal film (9) serving as a first electrode of an MIM-type capacitor. An insulating film (I3) has a structure in which insulating films (14 to 17) are layered on a second interconnection layer (L2) in this order. In the insulating film (15), a second electrode of the MIM-type capacitor is formed. The second electrode has a metal film (11) formed on the insulating film (14) and a metal film (10) formed on the metal film (11). A portion of the insulating film (14) which is sandwiched between the first electrode and the second electrode of the MIM-type capacitor serves as a capacitor dielectric film of the MIM-type capacitor. In the insulating film (I3), a third-level wire (W3) is formed.

Abstract: Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film 11 is formed on an upper surface of a third interlayer insulating film 10. Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film 11 and the third interlayer insulating film 10, respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film 9. Thereafter, a second interlayer insulating film 8 exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film 10.

Abstract: A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusion prevention film may be prepared from a silicon oxynitride film or a silicon oxide film containing Si—H bonds. A spacer film is formed on a surface of the F diffusion prevention film and its surface is flattened. A second layer metal wire is formed on a surface of the spacer film. Thus implemented is a semiconductor device comprising an F diffusion prevention film preventing F atoms contained in an SiOF film from diffusing into an upper metal wire with the F diffusion prevention film not etched in formation of the upper metal wire and a method of manufacturing a semiconductor device not directly polishing an SiOF film by CMP.

Abstract: A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusion prevention film may be prepared from a silicon oxynitride film or a silicon oxide film containing Si—H bonds. A spacer film is formed on a surface of the F diffusion prevention film and its surface is flattened. A second layer metal wire is formed on a surface of the spacer film. Thus implemented is a semiconductor device comprising an F diffusion prevention film preventing F atoms contained in an SiOF film from diffusing into an upper metal wire with the F diffusion prevention film not etched in formation of the upper metal wire and a method of manufacturing a semiconductor device not directly polishing an SiOF film by CMP.