Patents by Inventor Kinya Mitsumoto

Kinya Mitsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7623397
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Patent number: 7397880
    Abstract: In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Kinya Mitsumoto
  • Publication number: 20070188208
    Abstract: In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal. At this time, there are provided a first driving transistor capable of driving the output node of the first circuit on the basis of the second input signal, and a second driving transistor capable of driving the output node of the second circuit on the basis of the first input signal. The output nodes are driven using the first and second driving transistors, respectively.
    Type: Application
    Filed: April 9, 2007
    Publication date: August 16, 2007
    Inventor: Kinya Mitsumoto
  • Patent number: 7254068
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: August 7, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 7196424
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Publication number: 20060284296
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 21, 2006
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Publication number: 20060158918
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: March 15, 2006
    Publication date: July 20, 2006
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20060145266
    Abstract: A semiconductor integrated circuit, whose MOS transistors' layout structure is determined in consideration of the size of a device active region in a gate length direction, in which each transistor is formed. When stresses coming from the device isolation region, etc. are taken into account, for a circuit whose current driving power reduction caused by the stresses should be suppressed, the distance between the device isolation regions in the gate length direction may be selected so as to suppress the reduction in drain-source current. Further, for a circuit whose logical threshold voltage variations caused by the stresses should be suppressed, the distance between the device isolation regions in the gate length direction may be selected so that the variations in drain-source current caused by such stresses are balanced between the p-channel and n-channel transistors. Characteristic variations arising in the transistors owing to stresses coming from the device isolation region, etc.
    Type: Application
    Filed: January 3, 2006
    Publication date: July 6, 2006
    Inventors: Hirofumi Zushi, Kinya Mitsumoto
  • Patent number: 7068551
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: June 27, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20050232386
    Abstract: In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.
    Type: Application
    Filed: June 21, 2005
    Publication date: October 20, 2005
    Inventor: Kinya Mitsumoto
  • Patent number: 6909312
    Abstract: Phase synchronization is achieved by forming a first pulse to be synchronized with a reference pulse, a second pulse leading in phase for a certain period relative to said first pulse and a third pulse delayed in phase for a certain period from said first pulse; comparing said reference pulse with said first pulse in a first comparing; comparing said reference pulse with said second pulse and said third pulse in a second comparing; and forming a control voltage by giving priority to a comparison output of said second comparing with respect to a comparison output of said first comparing, matching the phase of said reference pulse with the phrase of said second pulse or said third pulse, and matching, after said matching of phases, the phrase of said reference pulse with the phase of said first pulse by forming said control, voltage from the comparison output of said first comparing.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: June 21, 2005
    Assignee: Renesas Technology Corp.
    Inventor: Kinya Mitsumoto
  • Publication number: 20050128839
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: February 1, 2005
    Publication date: June 16, 2005
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20050104175
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 19, 2005
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Publication number: 20050104642
    Abstract: In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal. At this time, there are provided a first driving transistor capable of driving the output node of the first circuit on the basis of the second input signal, and a second driving transistor capable of driving the output node of the second circuit on the basis of the first input signal. The output nodes are driven using the first and second driving transistors, respectively.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 19, 2005
    Inventor: Kinya Mitsumoto
  • Patent number: 6856559
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: February 15, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20040222831
    Abstract: Phase synchronization is achieved by forming a first pulse to be synchronized with a reference pulse, a second pulse leading in phase for a certain period relative to said first pulse and a third pulse delayed in phase for a certain period from said first pulse; comparing said reference pulse with said first pulse in a first comparing; comparing said reference pulse with said second pulse and said third pulse in a second comparing; and forming a control voltage by giving priority to a comparison output of said second comparing with respect to a comparison output of said first comparing, matching the phase of said reference pulse with the phrase of said second pulse or said third pulse, and matching, after said matching of phases, the phrase of said reference pulse with the phase of said first pulse by forming said control, voltage from the comparison output of said first comparing.
    Type: Application
    Filed: January 30, 2004
    Publication date: November 11, 2004
    Inventor: Kinya Mitsumoto
  • Publication number: 20040150055
    Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 5, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Masao Shinozaki, Takashi Akioka, Kinya Mitsumoto
  • Patent number: 6770941
    Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Masao Shinozaki, Takashi Akioka, Kinya Mitsumoto
  • Patent number: 6725325
    Abstract: A semiconductor memory device having a double data rate (DDR) mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for a reading operation with the lower bits of a specified memory address for a preceding writing operation, a second comparison logic circuit detecting if bits other than the lower bits match, and a third comparison logic circuit detecting that, when a match is obtained from the second comparison logic circuit, the lower bits of the specified memory address or a secondary memory address such as a burst address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation. The device may have a late write function and a register may be provided to latch single data rate (SDR)/DDR mode information.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 20, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Nishiyama, Kinya Mitsumoto, Takeshi Agari
  • Publication number: 20040027896
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co. , Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki