Abstract: Provided is a semiconductor device in which a snubber-circuit is incorporated and can realize downsizing of a power conversion circuit into which the semiconductor device is assembled, and is flexibly applicable to various electric equipment. A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, a plurality of trenches, a plurality of first electrodes disposed in a plurality of trenches by way of gate insulation films formed on side walls of the plurality of respective trenches, a plurality of second electrodes disposed above the plurality of first electrodes in a state where the second electrodes are spaced apart from the first electrodes, a plurality of first insulation regions, and a plurality of second insulation regions. The trenches, the first electrodes and the second electrodes are formed in stripes as viewed in a plan view. At least one of the plurality of second electrodes is connected to the drain electrode.

Abstract: A method of manufacturing a semiconductor device includes in the following order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a first gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the first gap; a shield electrode etching back step of forming a second gap; and a source electrode forming step of forming a source electrode.

Abstract: A method of manufacturing a semiconductor device includes in this order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step of forming a first insulation film; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the gap; and a source electrode forming step of forming a source electrode.

Abstract: A method of manufacturing a semiconductor device includes in the following order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a first gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the first gap; a shield electrode etching back step of forming a second gap; and a source electrode forming step of forming a source electrode.

Abstract: A method of manufacturing a semiconductor device includes in this order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step of forming a first insulation film; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the gap; and a source electrode forming step of forming a source electrode.

Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

Abstract: A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.

Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

Abstract: A semiconductor device SD includes a substrate SUB, a plurality of gate electrodes GE, a gate pad GEP, and gate interconnects GINC. The plurality of gate electrodes GE are formed in the substrate SUB, and extend electrically in parallel to each other. The gate pad GEP is formed in a region different from that in which the plurality of gate electrodes GE are formed in the substrate SUB. Each of a plurality of gate interconnects GINC connects the plurality of gate electrodes GE to the gate pad GEP.

Abstract: A semiconductor apparatus according to the present invention includes a first semiconductor layer of a first conductive type, a low concentration base region of a second conductive type formed on the first semiconductor layer, a gate electrode formed in a trench with insulating film on an inner surface of the trench that is formed to reach the first semiconductor layer from a surface of the low concentration base region, a source region of the first conductive type formed, contacting the insulating film, on a surface of the low concentration base region, a first high concentration base region, a second high concentration base region provided below and separated from the first concentration base region, and a third high concentration base region of the second conductive type included inside the low concentration base region, provided below and separated from the second high concentration base region.

Abstract: A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.

Abstract: A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.

Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: A semiconductor device 1 is a vertical MOSFET, and includes a plurality of unit cells 10 and a gate electrode 20. Each unit cell 10 includes a back-gate region 12 formed in the semiconductor substrate and a source region 14 formed in the semiconductor substrate so as to adjacently surround the back-gate region 12 in a plan-view. A portion of the back-gate region 12 is adjacent to the gate electrode 20. More specifically, the back-gate region 12 is in a rectangular plan-view shape, and adjacent to the gate electrode 20 at a pair of opposing sides out of the four sides thereof.

Abstract: A semiconductor device and method of manufacturing the same. The method includes: forming a trench in a silicon substrate; forming a first insulating film on a surface of the silicon substrate, the surface including an interior wall of the trench; forming a polysilicon film which plugged in the trench and covered on an entire surface of the silicon substrate; forming a second insulating film with oxidizing a portion of the polysilicon film disposed outside of the trench, and oxidizing a surface region of the silicon substrate located beneath the first insulating film disposed outside of the trench and a surface region of the polysilicon film in the trench; and forming an embedded polysilicon layer by removing the second insulating film so that the surface of the silicon substrate is partially exposed and the polysilicon film partially remains in the trench.

Abstract: A semiconductor apparatus includes a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed on a principal surface of the semiconductor substrate, a trench formed in a periphery of the base region, and an endless source region of the first conductivity type formed on a surface of the base region along the trench. In this semiconductor apparatus, the principal planes on side surfaces of the trench are composed of planes [100] and [110]. The interior angle of intersection of adjacent side surfaces of the trench is 135°. A minimum distance between the base region and the plane [110] facing each other through the source region is shorter than a minimum distance between the base region and the plane [100] facing each other through the source region.

Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.