Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.

Abstract: A semiconductor apparatus according to the present invention includes a P type base diffusion layer on an N type epitaxial layer, a plurality of gate electrodes reaching to the N? epitaxial layer, an N type source diffusion layer in a region near the gate electrodes, a first P+ type diffusion layer in a region where the N type source diffusion layer is not formed, and a second P+ type diffusion layer formed separated from the first P+ type diffusion layer, deeper than the first P+ type diffusion layer, and shallower than a bottom of a trench.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: A semiconductor device having an improved connecting reliability of an interconnect is presented via a simple and easy process, and further, a semiconductor device having a stable threshold voltage of a transistor that provide a stable electrical characteristic is also presented.

Abstract: A semiconductor device 1 is a vertical MOSFET, and includes a plurality of unit cells 10 and a gate electrode 20. Each unit cell 10 includes a back-gate region 12 formed in the semiconductor substrate and a source region 14 formed in the semiconductor substrate so as to adjacently surround the back-gate region 12 in a plan-view. A portion of the back-gate region 12 is adjacent to the gate electrode 20. More specifically, the back-gate region 12 is in a rectangular plan-view shape, and adjacent to the gate electrode 20 at a pair of opposing sides out of the four sides thereof.

Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Abstract: A semiconductor apparatus includes a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed on a principal surface of the semiconductor substrate, a trench formed in a periphery of the base region, and an endless source region of the first conductivity type formed on a surface of the base region along the trench. In this semiconductor apparatus, the principal planes on side surfaces of the trench are composed of planes [100] and [110]. The interior angle of intersection of adjacent side surfaces of the trench is 135°. A minimum distance between the base region and the plane [110] facing each other through the source region is shorter than a minimum distance between the base region and the plane [100] facing each other through the source region.

Abstract: A semiconductor substrate used for fabricating vertical devices, such as vertical MOSFET, capable of maintaining low ON-stage resistance and of ensuring a necessary level of OFF-stage breakdown voltage is provided. A heavily-doped arsenic layer of 0.5 to 3.0 ?m thick is inserted between a heavily-doped phosphorus layer 11 composing the drain of a vertical MOSFET and an n?-type drift layer. The heavily-doped arsenic layer functions as a barrier layer which prevents phosphorus from diffusing from the heavily-doped phosphorus layer into the n?-type drift layer. This is successful in maintaining spreading of the depletion layer during OFF time of the vertical MOSFET to thereby improve the OFF-stage breakdown voltage, and in maintaining the low ON-stage resistance.

Abstract: In a vertical-type metal insulator field effect transistor device having a first conductivity type drain region layer, a plurality of second conductivity type base regions are produced and arranged in the first conductivity type drain region layer, and a first conductivity type source region is produced in each of the second conductivity type base regions. Both a gate insulating layer and a gate electrode layer are formed on the first conductivity type drain region layer such that a plurality of unit transistor cells are produced in conjunction with the second conductivity type base regions and the first conductivity type source regions, and each of the unit transistor cells includes respective span portions of the gate insulating layer and the gate electrode layer, which bridge a space between the first conductivity type source regions formed in two adjacent second conductivity base regions.

Abstract: A vertical field effect transistor includes an N.sup.+semiconductor substrate and an N.sup.−epitaxial layer deposited thereon and having lower dopant concentration than the semiconductor substrate, and is configured to have a plurality of unit cell transistors formed in the N.sup.−epitaxial layer and arranged in the epitaxial layer in longitudinal and lateral directions. The unit cell transistor includes a trench formed to have a depth X.sub.a and a width W, and further a gate electrode 25 formed within the trench and interposing a gate insulating film that has a thickness T.sub.OX and formed between the gate electrode and the surface of the trench. Moreover, the unit cell transistor includes a P-type base region having a depth X.sub.b, a source region, a heavily doped P-type base region formed in a central portion of the cell transistor and having a depth X.sub.

Abstract: A vertical field effect transistor includes an N.sup.+ semiconductor substrate and an N. sup.− epitaxial layer deposited thereon and having lower dopant concentration than the semiconductor substrate, and is configured to have a plurality of unit cell transistors formed in the N.sup.− epitaxial layer and arranged in the epitaxial layer in longitudinal and lateral directions. The unit cell transistor includes a trench formed to have a depth X.sub.a and a width W, and further a gate electrode 25 formed within the trench and interposing a gate insulating film that has a thickness T.sub.OX and formed between the gate electrode and the surface of the trench. Moreover, the unit cell transistor includes a P-type base region having a depth X.sub.b, a source region, a heavily doped P-type base region formed in a central portion of the cell transistor and having a depth X.sub.

Abstract: In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is mainly formed by an Al alloy layer containing Cu.