Abstract: Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.

Abstract: An apparatus includes a convergence detector circuit coupled to an error locator polynomial generator circuit. The convergence detector circuit includes at least two computation circuits configured to generate at least two convergence signals based on a mutual error locator polynomial from the error locator polynomial generator circuit and on at least two different sets of syndromes. Each of the different sets of syndromes corresponds to a different one of the convergence signals.

Abstract: A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.

Abstract: Systems and methods for determining a physical block address (PBA) of a non-volatile memory (NVM) to enable a data access of a corresponding logical block address (LBA) are described. One such method includes generating a first physical block address (PBA) candidate from a LBA using a first function; generating a second physical block address (PBA) candidate from the LBA using a second function; and selecting either the first PBA candidate or the second PBA candidate for the data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

Abstract: Systems and methods for wear leveling in non-volatile memories (NVMs) are disclosed. One such system includes a cumulative control state determiner configured to determine a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, an access network configured to translate a LBA to a PBA based on the cumulative control state, and a background swap scheduler configured to swap PBAs assigned to preselected LBAs based on a control state. One such method involves determining a cumulative control state indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of an NVM, translating a LBA to a PBA based on the cumulative control state, and swapping PBAs assigned to preselected LBAs based on a control state.

Abstract: The present disclosure generally relates to methods for managing bad pages in storage devices. When a page is bad or faulty, a spare page is used to store the data because the bad or faulty page is unreliable for data storage. When the time comes to read the data from the bad page or write data onto the page, there needs to be some direction to the spare page. The bad or faulty page may contain a pointer to direct to the location of the spare page or metadata containing directions to the location of the spare page. A hash function may be used to calculate that the stored data in the bad or faulty page is incorrect and, once decoded, provide direction to the spare page. By using pointers, metadata or hash functions, additional data tables are unnecessary and data storage is more efficient.

Abstract: Systems and methods for wear leveling in non-volatile memories (NVMs) are illustrated. One such system includes a first non-volatile memory configured to store information from a host, a second non-volatile memory storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states, an access network configured to translate LBAs to PBAs based on the plurality of cumulative control states, a background swap scheduler configured to swap PBAs assigned to LBAs based on the plurality of control states, and a controller configured to sequentially advance through the plurality of cumulative control states and the plurality of control states.

Abstract: Systems and methods for determining a cumulative control state for mapping logical block addresses (LBAs) to physical block addresses (PBAs) are disclosed. One such system includes a bitonic network including first switches and configured to receive a first randomly ordered list and random switch settings, determine a permutation of the first randomly ordered list using the random switch settings at the first switches, where the permutation includes a second randomly ordered list, and output the second randomly ordered list; a bitonic sorter including second switches and configured to receive the second randomly ordered list, sort the second randomly ordered list, and output settings of the second switches used to achieve the sort, where the second switch settings define a cumulative control state; and an access network configured to determine a PBA of a non-volatile memory (NVM) to enable a data access of a corresponding LBA using the cumulative control state.

Abstract: Described herein are systems and methods that that mitigate avalanche photodiode (APD) blinding and allow for improved accuracy in the detection of a multi-return light signal. A blinding spot may occur due to saturation of a primary APD. The systems and methods include the incorporation of a redundant APD and the utilization of time diversity and space diversity. Detection by the APDs is activated by a bias signal. The redundant APD receives a time delayed bias signal compared to the primary APD. Additionally, the redundant APD is positioned off the main focal plane in order to attenuate an output of the redundant APD. With attenuation, the redundant APD may not saturate and may have a successful detection during the blinding spot of the primary APD. Embodiments may include multiple primary APDs and multiple secondary APDs.

Abstract: Described herein are systems and methods that may efficiently detect multi-return light signals. A light detection and ranging system, such as a LIDAR system, may fire a laser beam that may hit multiple objects with a different distance in one line, causing multi-return light signals to be received by the system. Multi-return detectors may be able to analyze the peak magnitude of a plurality of peaks in the return signals and determine a multitude of peaks, such as the first peak, the last peak and the maximum peak. One embodiment to detect the multi-return light signals may be a multi-return recursive matched filter detector. This detector comprises a matched filter, peak detector, centroid calculation and a zeroing out function. Other embodiments may be based on a maximum finder that algorithmically selects the highest magnitude peaks from samples of the return signal and buffers for regions of interests peaks.

Abstract: Described herein are systems and methods that determines a centroid of a waveform in a high noise environment. In one embodiment, the method may include determining a damping threshold and a noise-exclusion threshold for a waveform that define a three tier dynamic range for the waveform comprising a noise-exclusion region, damping region and a full region. The noise-exclusion threshold may be less than the damping threshold. Weights for each of the mass scalars may be determined based on the three tier dynamic range. The centroid may be determined based on the determined weights and their corresponding position vectors.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.

Abstract: Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.

Abstract: The present disclosure generally relates to methods of reading data from a memory device using non-binary ECCs. The memory device includes multiple memory cells where each memory cell has multiple pages that are arranged in distinct layouts for physical addresses thereof. When a read request is received from a host device to obtain data from a specific page of a specific memory cell of a memory device, rather than reading the data from all pages of the memory cell, the data can be read from just the desired page and then decoded. Following decoding, the data can be delivered to the host device. Because only the data from a specific page of a memory cell is read, rather than the entire memory cell, the read latency is reduced when compared to reading the entire memory cell.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. A method and system for decoding low density parity check (“LDPC”) codes. An LDPC code decoder includes decoding circuitry configured to process blocks of an LDPC matrix. The decoding circuitry includes a control unit that controls processing by the decoding circuitry. The control unit is configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order.

Abstract: The embodiments disclosed herein include an interconnection network that is configured to provide data communication between storage processing units. The disclosed interconnection network can be particularly effective when the storage processing units are configured to locally perform scientific computations. The disclosed interconnection network can enable localized, high throughput, and low latency data communication between storage processing units without overloading the host system.

Abstract: Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such system includes a host having a processing task, a plurality of storage processing units (SPUs), a host interface configured to enable communications between the host and each of the plurality of SPUs, and an interconnection network coupled to at least two of the plurality of SPUs, where the host is configured to command at least one of the plurality of SPUs to perform the processing task, and command the interconnection network to couple two or more of the plurality of SPUs.

Abstract: Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Abstract: Systems and methods are disclosed for a journal for a storage class memory device. The storage class memory device may execute an access command for a first page in the storage class memory device. The storage class memory device may also determine whether a failure occurred while executing the access command. The storage class memory device may create an entry in a journal for the storage class memory device if a failure occurred while executing the access command. The storage class memory device may refrain from creating the entry if a failure does not occur while executing the access command.

Abstract: The present disclosure generally relates to methods for managing bad pages in storage devices. When a page is bad or faulty, a spare page is used to store the data because the bad or faulty page is unreliable for data storage. When the time comes to read the data from the bad page or write data onto the page, there needs to be some direction to the spare page. The bad or faulty page may contain a pointer to direct to the location of the spare page or metadata containing directions to the location of the spare page. A hash function may be used to calculate that the stored data in the bad or faulty page is incorrect and, once decoded, provide direction to the spare page. By using pointers, metadata or hash functions, additional data tables are unnecessary and data storage is more efficient.