Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic shifter. The R select unit provides an R message by selecting from a plurality of possible R message values. The Q message memory stores a Q message until an R message is generated by a CNU, the Q message and the R message are combined to provide a P message. The cyclic shifter shifts the P message.

Abstract: An integrated circuit comprises logic circuitry, organized in a multi-level hierarchy of modules. The integrated circuit comprises multiple sensing circuits. In operation, each sensing circuit senses an instantaneous current consumption IC of a respective one of the modules that draws current entirely through that sensing circuit. The integrated circuit comprises a concealing circuit for each of the sensing circuits. In operation, the concealing circuit receives as input a voltage VC corresponding to the sensed instantaneous current consumption IC of its respective module, and the concealing circuit dissipates an instantaneous power PL such that an instantaneous power sum PTOTAL of the instantaneous power PL and the instantaneous power PC to be dissipated by its respective module is substantially independent of activity of its respective module.

Abstract: A hardware countermeasure for a cryptographic hardware module of a computing device is provided. The hardware countermeasure may include a noise-sample generator and a distributed buffer network co-located with the cryptographic module. The noise-sample generator may take as input data samples to be processed by the cryptographic hardware module and generate as output a non-Gaussian noise-sample for each of the input data samples. The distributed buffer network may take as input the non-Gaussian noise-samples and generate a non-Gaussian noise output corresponding to each of the non-Gaussian noise-samples.

Abstract: A method and system for decoding low density parity check (“LDPC”) codes. An LDPC decoder includes a control unit that controls decoder processing, the control unit causing the decoder to process the blocks of a low density parity check (“LDPC”) matrix out of order. A decoder embodiment may process the layers of the LDPC matrix out of order and/or perform partial state processing on out of order blocks of the LDPC matrix and/or generate R messages out of order.

Abstract: A hardware countermeasure for a cryptographic hardware module of a computing device is provided. The hardware countermeasure may include a noise-sample generator and a distributed buffer network co-located with the cryptographic module. The noise-sample generator may take as input data samples to be processed by the cryptographic hardware module and generate as output a non-Gaussian noise-sample for each of the input data samples. The distributed buffer network may take as input the non-Gaussian noise-samples and generate a non-Gaussian noise output corresponding to each of the non-Gaussian noise-samples.

Abstract: An integrated circuit comprises logic circuitry, organized in a multi-level hierarchy of modules. The integrated circuit comprises multiple sensing circuits. In operation, each sensing circuit senses an instantaneous current consumption IC of a respective one of the modules that draws current entirely through that sensing circuit. The integrated circuit comprises a concealing circuit for each of the sensing circuits. In operation, the concealing circuit receives as input a voltage VC corresponding to the sensed instantaneous current consumption IC of its respective module, and the concealing circuit dissipates an instantaneous power PL such that an instantaneous power sum PTOTAL of the instantaneous power PL and the instantaneous power PC to be dissipated by its respective module is substantially independent of activity of its respective module.

Abstract: An integrated circuit comprises logic circuitry driven by a clock and reference circuitry. In operation, logic elements of the reference circuitry are synchronized to the clock. In operation, a first sensing circuit outputs a voltage VC proportional to an instantaneous current consumption IC of the logic circuitry, and a second sensing circuit outputs a voltage VR proportional to an instantaneous fluctuating current consumption IR of the reference circuitry. In operation, differential circuitry outputs a voltage difference ?VR?VC between a scaled-up version ?VR of the voltage VR and the voltage VC, the scaled-up version scaled to approximately the scale of the voltage VC. In operation, a square root circuit receives the voltage difference as input and outputs a square root of the voltage difference. A current source is controllable by the output of the square root circuit to generate current through a dissipative load.