Patents by Inventor Kirby MAXEY

Kirby MAXEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230086499
    Abstract: Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Kirby MAXEY, Ashish Verma PENUMATCHA, Kevin P. O'BRIEN, Chelsey DOROW, Uygar E. AVCI, Sudarat LEE, Carl NAYLOR, Tanay GOSAVI
  • Publication number: 20220199799
    Abstract: Thin film transistors having boron nitride integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a first gate stack above a substrate. A 2D channel material layer is above the first gate stack. A second gate stack is above the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack and in contact with the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack and in contact with the 2D channel material layer. A hexagonal boron nitride (hBN) layer is included between the first gate stack and the 2D channel material layer, between the second gate stack and the 2D channel material layer, or both.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Kevin P. O'BRIEN, Chelsey DOROW, Carl NAYLOR, Kirby MAXEY, Tanay GOSAVI, Uygar E. AVCI, Ashish Verma PENUMATCHA, Chia-Ching LIN, Shriram SHIVARAMAN, Sudarat LEE
  • Publication number: 20220149192
    Abstract: Thin film transistors having electrostatic double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A 2D channel material layer is on the first gate stack. A second gate stack is on a first portion of the 2D channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the 2D channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the 2D channel material layer. A gate electrode of the first gate stack extends beneath a portion of the first conductive contact and beneath a portion of the second conductive contact.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Inventors: Kirby MAXEY, Ashish Verma PENUMATCHA, Carl NAYLOR, Chelsey DOROW, Kevin P. O'BRIEN, Shriram SHIVARAMAN, Tanay GOSAVI, Uygar E. AVCI, Sudarat LEE
  • Publication number: 20210408288
    Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Inventors: Kevin P. O'Brien, Carl NAYLOR, Chelsey DOROW, Kirby MAXEY, Tanay GOSAVI, Ashish Verma PENUMATCHA, Shriram SHIVARAMAN, Chia-Ching LIN, Sudarat LEE, Uygar E. AVCI
  • Publication number: 20210391478
    Abstract: Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Kirby MAXEY, Chelsey DOROW, Kevin P. O'BRIEN, Carl NAYLOR, Ashish Verma PENUMATCHA, Tanay GOSAVI, Uygar E. AVCI, Shriram SHIVARAMAN