Patents by Inventor Kirk D. Prall

Kirk D. Prall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-volatile memory cell device and methods
    Patent number: 7897470
    Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Relaxed metal pitch memory architectures
    Patent number: 7881113
    Abstract: A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: February 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Lyle D. Jones, Roger W. Lindsay, Kirk D. Prall
  • MEMORY CELLS CONFIGURED TO ALLOW FOR ERASURE BY ENHANCED F-N TUNNELING OF HOLES FROM A CONTROL GATE TO A CHARGE TRAPPING MATERIAL
    Publication number: 20100264482
    Abstract: Memory cells including a control gate, a charge trapping material, and a charge blocking material between the control gate and the charge trapping material. The charge blocking material is configured to allow for erasure of the memory cell by enhanced F-N tunneling of holes from the control gate to the charge trapping material.
    Type: Application
    Filed: July 2, 2010
    Publication date: October 21, 2010
    Inventors: Arup Bhattacharyya, Kirk D. Prall, Luan C. Tran
  • PITCH MULTIPLICATION SPACERS AND METHODS OF FORMING THE SAME
    Publication number: 20100267240
    Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 21, 2010
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
    Publication number: 20100244117
    Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
    Type: Application
    Filed: June 8, 2010
    Publication date: September 30, 2010
    Inventors: Kirk D. Prall, Leonard Forbes
  • RIGID SEMICONDUCTOR MEMORY HAVING AMORPHOUS METAL OXIDE SEMICONDUCTOR CHANNELS
    Publication number: 20100213458
    Abstract: Rigid semiconductor memory using amorphous metal oxide semiconductor channels are useful in the production of thin-film transistor memory devices. Such devices include single-layer and multi-layer memory arrays of volatile or non-volatile memory cells. The memory cells can be formed to have a gate stack overlying an amorphous metal oxide semiconductor, with amorphous metal oxide semiconductor channels.
    Type: Application
    Filed: February 23, 2009
    Publication date: August 26, 2010
    Inventor: Kirk D. Prall
  • Pitch multiplication spacers and methods of forming the same
    Patent number: 7776744
    Abstract: Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • NROM memory cell, memory array, related devices and methods
    Patent number: 7750389
    Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: July 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Leonard Forbes
  • Band-engineered multi-gated non-volatile memory device with enhanced attributes
    Patent number: 7749848
    Abstract: Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: July 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Kirk D. Prall, Luan C. Tran
  • Method of fabricating memory transistor
    Patent number: 7745283
    Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: June 29, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kirk D. Prall
  • PROGRAMMING METHODS FOR MULTI-LEVEL MEMORY DEVICES
    Publication number: 20100142273
    Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
    Type: Application
    Filed: February 3, 2010
    Publication date: June 10, 2010
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: CHUN CHEN, Kirk D. Prall
  • Programming methods for multi-level memory devices
    Patent number: 7684249
    Abstract: A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: March 23, 2010
    Assignee: Round Rock Research, LLC
    Inventors: Chun Chen, Kirk D. Prall
  • Memory transistor and methods
    Patent number: 7651911
    Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: January 26, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kirk D. Prall
  • Semiconductor Constructions
    Publication number: 20090309151
    Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.
    Type: Application
    Filed: August 20, 2009
    Publication date: December 17, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • NON-VOLATILE MEMORY CELL DEVICE AND METHODS
    Publication number: 20090263962
    Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.
    Type: Application
    Filed: July 1, 2009
    Publication date: October 22, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Methods of forming semiconductor constructions and flash memory cells
    Patent number: 7588982
    Abstract: Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some embodiments may include a method in which a semiconductor substrate is provided to have a plurality of active area locations. Floating gates are formed over the active area locations, with the floating gates having widths that are entirely sub-lithographic. Adjacent floating gates are spaced from one another by gaps. Dielectric material and control gate material are formed over the floating gates and within the gaps. Some embodiments may include a construction in which a pair of adjacent floating gates are over a pair of adjacent active areas, with the floating gates being spaced from one another by a distance which is greater than a distance that the active areas are spaced from one another.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • Non-volatile memory cell device and methods
    Patent number: 7560769
    Abstract: A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 14, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kirk D. Prall
  • NROM memory cell, memory array, related devices and methods
    Patent number: 7541242
    Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: June 2, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Leonard Forbes
  • NROM memory cell, memory array, related devices and methods
    Patent number: 7535048
    Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: May 19, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kirk D. Prall, Leonard Forbes
  • Programming methods for multi-level flash EEPROMs
    Publication number: 20090046508
    Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 19, 2009
    Inventors: Chun Chen, Kirk D. Prall