Patents by Inventor Kirk David Peterson
Kirk David Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136372Abstract: A pixel for an ambient light and/or color sensor includes a plurality of pinned photodiodes. The pixel also includes a floating diffusion region. A ratio of an active area of the plurality of pinned photodiodes to an area of the floating diffusion region is greater than 150.Type: ApplicationFiled: February 22, 2022Publication date: April 25, 2024Inventors: Benjamin Joseph SHEAHAN, Jong Mun PARK, Robert VAN ZEELAND, Kirk David PETERSON, Wern Ming KOE, George Richard KELLY, Mario MANNINGER, Dong-Long LIN, Pascale FRANCIS, Koen RUYTHOOREN
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Publication number: 20220139909Abstract: A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Inventors: Terence B. Hook, Baozhen Li, Kirk David Peterson, Junli Wang
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Patent number: 11251179Abstract: A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.Type: GrantFiled: June 30, 2016Date of Patent: February 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Baozhen Li, Kirk David Peterson, Junli Wang
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Patent number: 10784159Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.Type: GrantFiled: February 28, 2019Date of Patent: September 22, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
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Publication number: 20190363013Abstract: A semiconductor device includes a first dielectric layer including a first contact hole, a second dielectric layer formed on the first dielectric layer, and including a second contact hole aligned with the first contact hole, and a reflowed copper layer formed in the first and second contact holes.Type: ApplicationFiled: February 28, 2019Publication date: November 28, 2019Inventors: Lawrence A. CLEVENGER, Baozhen LI, Kirk David PETERSON, John E. SHEETS, II, Junli WANG, Chih-Chao YANG
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Patent number: 10256145Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.Type: GrantFiled: December 29, 2017Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
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Patent number: 9966308Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.Type: GrantFiled: October 4, 2016Date of Patent: May 8, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
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Publication number: 20180122697Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
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Patent number: 9941300Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.Type: GrantFiled: December 16, 2015Date of Patent: April 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: John Joseph Ellis-Monaghan, Terence B Hook, Kirk David Peterson
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Publication number: 20180096890Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventors: Lawrence A. CLEVENGER, Baozhen LI, Kirk David Peterson, John E. SHEETS, II, Junli WANG, Chih-Chao YANG
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Publication number: 20180006025Abstract: A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Baozhen Li, Kirk David Peterson, Junli Wang
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Publication number: 20170179156Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Inventors: John Joseph Ellis-Monaghan, Terence B. Hook, Kirk David Peterson
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Patent number: 8238032Abstract: A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.Type: GrantFiled: February 19, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Kirk David Peterson, Jed Hickory Rankin
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Patent number: 7716516Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.Type: GrantFiled: June 21, 2006Date of Patent: May 11, 2010Assignees: Sony Computer Entertainment Inc., International Business Machines Corporation, Toshiba America Electronic Components, Inc.Inventors: Yosuke Muraki, Tetsuji Tamura, Iwao Takiguchi, Makoto Aikawa, Eskinder Hailu, Byron Lee Krauter, Stephen Douglas Weitzel, Jieming Qi, Kazuhiko Miki, David William Boerstler, Gilles Gervais, Kirk David Peterson, Robert Walter Berry, Jr., Sang Hoo Dhong
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Patent number: 7696586Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.Type: GrantFiled: July 18, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
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Patent number: 7687340Abstract: A semiconductor structure fabrication method. First, a semiconductor structure is provided including (a) a semiconductor block having a first semiconductor material doped with a first doping polarity and having a first lattice orientation, and (b) a semiconductor region on the semiconductor block, wherein the semiconductor region is physically isolated from the semiconductor block by a dielectric region, and wherein the semiconductor region includes a second semiconductor material (i) doped with a second doping polarity opposite to the first doping polarity and (ii) having a second lattice orientation different from the first lattice orientation. Next, first and second gate stacks are formed on the semiconductor block and the semiconductor region, respectively. Then, (i) first and second S/D regions are simultaneously formed in the semiconductor block on opposing sides of the first gate stack and (ii) first and second discharge prevention semiconductor regions in the semiconductor block.Type: GrantFiled: September 4, 2007Date of Patent: March 30, 2010Assignee: International Business Machines CorporationInventors: James William Adkisson, Jeffrey Peter Gambino, Alain Loiseau, Kirk David Peterson
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Patent number: 7609542Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.Type: GrantFiled: October 17, 2007Date of Patent: October 27, 2009Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Todd Alan Christensen, Travis Reynold Hebig, Kirk David Peterson
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Publication number: 20090027946Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Inventors: Chad Allen Adams, Todd Alan Christensen, Travis Reynold Hebig, Kirk David Peterson
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Publication number: 20090027945Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.Type: ApplicationFiled: October 17, 2007Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Todd Alan Christensen, Travis Reynold Hebig, Kirk David Peterson
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Patent number: 7480170Abstract: A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO). A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.Type: GrantFiled: July 25, 2007Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Todd Alan Christensen, Travis Reynold Hebig, Kirk David Peterson