Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and a top surface; the non-printable region comprising a second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and a top surface; and a capping layer on the sidewalls of the first opaque regions and the sidewalls of the second opaque region.

Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

Abstract: A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

Abstract: A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: The present invention includes a plurality of FETs (211, 212, 213, 214, 215, 216, 217) including an operational amplifier with additional FETs (218, 219, 220,221) arranged as current mirrors, and a sense FET (101), and a current sensed at FET (101) is amplified, compared to a reference signal, the difference current derived from the amplified sense current and reference signal being amplified and provided at an output for use in control applications.

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2layer in said structure.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material.

Abstract: A method for removing a formation of oxide of titanium that is generated as a by product of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65 ° C. combined with a 3 minute period of application.

Abstract: A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H2O), ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), wherein the NH4OH and the H2O2 each comprise approximately 4% of the total reagent volume. An effective temperature is 65° C. combined with a 3 minute period of application.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.