Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.

Abstract: Embodiments of the present invention are directed to the implantation of composite tunnel field effect transistors (TFETs) in a nanosheet process. In a non-limiting embodiment of the invention, a first source or drain region is formed having a first composition and a first doping type. A second source or drain region is formed having a second composition and a second doping type opposite the first doping type. A first composite channel structure is formed between the first source or drain region and the second source or drain region. The first composite channel structure includes a first nanosheet trimmed to expose extension portions of the first source or drain region and extension portions of the second source or drain region. The first composite channel structure further includes a first channel epitaxy wrapping around the trimmed first nanosheet. The first channel epitaxy is connected laterally to the extension portions.

Abstract: A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.

Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes providing a cavity structure comprising a seed area with a seed material. The method further includes growing, within the cavity structure, a quantum dot structure in a first growth direction from a seed surface of the seed material and growing, in the first growth direction, a first embedding layer on a first surface of the quantum dot structure. The method further includes removing the seed material and growing, within the cavity structure, on a second surface of the quantum dot structure, a second embedding layer in a second growth direction. The second surface of the quantum dot structure is different from the first surface of the quantum dot structure and the second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.

Abstract: One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

Abstract: One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device having a co-integrated RTD and HEMT. A semiconductor device can comprise an RTD and an HEMT that are co-integrated along a substrate. A fabrication method can comprise providing a heterostructure comprising a plurality of transistor layers of an HEMT, forming on the vertical stack a template structure comprising an opening, a cavity and a seed structure, the seed structure comprising a seed material and a seed surface, and growing a plurality of diode layers of an RTD within the cavity of the template structure from the seed surface, wherein the RTD and HEMT are co-integrated along a substrate.

Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.

Abstract: A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.

Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes steps of providing a cavity structure, the cavity structure including a seed area including a seed material. The method further includes growing, within the cavity structure, a first embedding layer in a first growth direction from a seed surface of the seed material. The method includes further steps of removing the seed material, growing, in a second growth direction, from a seed surface of the first embedding layer, a quantum dot structure and growing, within the cavity structure, on a surface of the quantum dot structure, a second embedding layer in the second growth direction. The second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.

Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes providing a cavity structure comprising a seed area with a seed material. The method further includes growing, within the cavity structure, a quantum dot structure in a first growth direction from a seed surface of the seed material and growing, in the first growth direction, a first embedding layer on a first surface of the quantum dot structure. The method further includes removing the seed material and growing, within the cavity structure, on a second surface of the quantum dot structure, a second embedding layer in a second growth direction. The second surface of the quantum dot structure is different from the first surface of the quantum dot structure and the second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.

Abstract: The invention relates to a method for fabricating a semiconductor device. The method includes steps of providing a cavity structure, the cavity structure including a seed area including a seed material. The method further includes growing, within the cavity structure, a first embedding layer in a first growth direction from a seed surface of the seed material. The method includes further steps of removing the seed material, growing, in a second growth direction, from a seed surface of the first embedding layer, a quantum dot structure and growing, within the cavity structure, on a surface of the quantum dot structure, a second embedding layer in the second growth direction. The second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.

Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.

Abstract: The invention relates to a method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure. The method further comprises replacing the first material within the predefined part of the photonic crystal structure with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. The invention further relates to devices obtainable by such a method.

Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Abstract: A method forms heterogeneous complementary FETs and a related semiconductor structure. The method comprises forming a layered nanosheet stack comprising two layers of a first channel material alternating with two layers of a second channel material, depositing a dielectric layer on a top layer of the nanosheet stack, and forming a checkered mask material with at least a first and a second row above the dielectric material. The first and the second row are distanced from each other. The method removes the first channel material and the second channel material outside an area of the checkered mask material, resulting in the at least a first row of pillars and a second row of pillars of layered nanosheet stacks. The method selectively removes in each of the pillars of the first stripe the second channel material.

Abstract: A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.

Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.

Abstract: The invention relates to a method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure. The method further comprises replacing the first material within the predefined part of the photonic crystal structure with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. The invention further relates to devices obtainable by such a method.

Abstract: Embodiments of the invention relate to a plasmonic laser including a substrate and a coaxial plasmonic cavity formed on the substrate and adapted to facilitate a plasmonic mode. The plasmonic laser further includes an electrical pumping circuit configured to electrically pump the plasmonic laser. The coaxial plasmonic cavity includes a peripheral plasmonic ring structure, a central plasmonic core and a gain structure arranged between the peripheral plasmonic ring structure and the central plasmonic core. The gain structure includes one or more ring-shaped quantum wells as gain material. The one or more ring-shaped quantum wells have a surface that is aligned orthogonal to a surface of the substrate. The electrical pumping circuit is configured to pump the plasmonic laser via the peripheral plasmonic ring structure and the central plasmonic core.