Abstract: A cavity structure comprises one or more seed surfaces, a first growth path for the growth of a first semiconductor structure from one of the one or more seed surfaces and a second growth path for the growth of a second semiconductor structure from one of the one or more seed surfaces. The cavity structure further comprises at least one opening for supplying precursor materials to the cavity structure. A method can include selectively growing the first semiconductor structure along the first growth path and selectively growing the second semiconductor structure along the second growth path. The first semiconductor structure has a first growth front and the second semiconductor structure has a second growth front. The method can further include merging the first and the second growth front at a border area of the first and the second semiconductor structure.

Abstract: The present disclosure relates to a method for fabricating an FET structure. The method includes forming on a substrate a first semiconductor structure and an insulator structure covering the first semiconductor structure with a first insulator layer, forming on the first insulator layer a sacrificial layer extending to a reference plane, forming a second insulator layer on the reference plane, forming a first cavity through the second insulator layer, the sacrificial layer and the first insulator layer, thus exposing a surface of the first semiconductor structure, filling the first cavity with a second semiconductor structure extending from the surface at least up to the first reference plane, forming a third semiconductor structure on the second semiconductor structure, selectively removing the sacrificial layer, thus forming a second cavity, and filling the second cavity with a gate structure.

Abstract: The present disclosure relates to a method for fabricating a field-effect transistor structure on a substrate. The method includes forming a first semiconductor structure on the substrate, forming above the first semiconductor structure a gate structure that comprises a spacer layer laterally terminating the gate structure and has a lower etch rate than the first semiconductor structure with respect to a predetermined etchant, forming an undercut below the spacer layer by recessing the first semiconductor structure using the etchant, the undercut extending laterally below the spacer layer by not more than the thickness of the spacer layer, forming on the first semiconductor structure a second semiconductor structure filling the undercut, and forming a third semiconductor structure above the first semiconductor structure, wherein one of the second and third semiconductor structures forms the source of the field-effect transistor structure and the other one forms the drain.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A method for fabricating an ellipsoidal or semi-ellipsoidal semiconductor structure includes steps of providing a semiconductor substrate and fabricating an ellipsoidal or semi-ellipsoidal cavity structure on the semiconductor substrate. The cavity structure encompasses a seed surface of the semiconductor substrate. The method includes a further step of growing the ellipsoidal or semi-ellipsoidal semiconductor structure within the ellipsoidal or semi-ellipsoidal cavity structure from the seed surface of the semiconductor substrate. Fabricating the cavity structure includes arranging a droplet comprising a sacrificial material on the semiconductor substrate, forming a layer of a coating material on the semiconductor substrate and the droplet, and selectively removing the sacrificial material of the droplet to expose the cavity structure.

Abstract: A method for fabricating an ellipsoidal or semi-ellipsoidal semiconductor structure includes steps of providing a semiconductor substrate and fabricating an ellipsoidal or semi-ellipsoidal cavity structure on the semiconductor substrate. The cavity structure encompasses a seed surface of the semiconductor substrate. The method includes a further step of growing the ellipsoidal or semi-ellipsoidal semiconductor structure within the ellipsoidal or semi-ellipsoidal cavity structure from the seed surface of the semiconductor substrate. Fabricating the cavity structure includes arranging a droplet comprising a sacrificial material on the semiconductor substrate, forming a layer of a coating material on the semiconductor substrate and the droplet, and selectively removing the sacrificial material of the droplet to expose the cavity structure.

Abstract: A cavity structure comprises one or more seed surfaces, a first growth path for the growth of a first semiconductor structure from one of the one or more seed surfaces and a second growth path for the growth of a second semiconductor structure from one of the one or more seed surfaces. The cavity structure further comprises at least one opening for supplying precursor materials to the cavity structure. A method can include selectively growing the first semiconductor structure along the first growth path and selectively growing the second semiconductor structure along the second growth path. The first semiconductor structure has a first growth front and the second semiconductor structure has a second growth front. The method can further include merging the first and the second growth front at a border area of the first and the second semiconductor structure.

Abstract: Embodiments of the invention relate to a plasmonic laser including a substrate and a coaxial plasmonic cavity formed on the substrate and adapted to facilitate a plasmonic mode. The plasmonic laser further includes an electrical pumping circuit configured to electrically pump the plasmonic laser. The coaxial plasmonic cavity includes a peripheral plasmonic ring structure, a central plasmonic core and a gain structure arranged between the peripheral plasmonic ring structure and the central plasmonic core. The gain structure includes one or more ring-shaped quantum wells as gain material. The one or more ring-shaped quantum wells have a surface that is aligned orthogonal to a surface of the substrate. The electrical pumping circuit is configured to pump the plasmonic laser via the peripheral plasmonic ring structure and the central plasmonic core.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A plasmonic quantum well laser may be provided. The plasmonic quantum well laser includes a plasmonic waveguide and a p-n junction structure extends orthogonally to a direction of plasmon propagation along the plasmonic waveguide. Thereby, the p-n junction is positioned atop a dielectric material having a lower refractive index than material building the p-n junction, and the quantum well laser is electrically actuated. A method for building the plasmonic quantum well laser is also provided.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Abstract: Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×104 nm2. The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.

Abstract: A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.

Abstract: The present invention relates to a semiconductor device (1) comprising: at least a nanowire (2) configured to comprise: at least a source region (3) comprising a corresponding source semiconductor material, at least a drain region (4) comprising a corresponding drain semiconductor material and at least a channel region (5) comprising a corresponding channel semiconductor material, the channel region (5) being arranged between the source region (3) and the drain region (4), at least a gate electrode (6) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of the channel region (5), and at least a strain gate (7) that is arranged relative to the nanowire (2) to circumferentially surround at least a part of a segment of the nanowire (2), the strain gate (7) being configured to apply a strain to the nanowire segment (8), thereby to facilitate at least an alteration of the energy bands corresponding to the source region (3) relative to the energy bands corresponding to the ch

Abstract: A tunnel field-effect transistor including at least: a source region including a corresponding source semiconductor material; a drain region including a corresponding drain semiconductor material, and a channel region including a corresponding channel semiconductor material, which is arranged between the source region and the drain region. The tunnel field-effect transistor further includes at least: a source-channel gate electrode provided on an interface between the source region and the channel region; an insulator corresponding to the source-channel gate electrode that is provided between the source-channel gate electrode and the interface between the source region and the channel region; a drain-channel gate electrode provided on an interface between the drain region and the channel region; and an insulator corresponding to the drain-channel gate electrode that is provided between the drain-channel gate electrode and the interface between the drain region and the channel region.