Patents by Inventor Kishore K. Chakravorty
Kishore K. Chakravorty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7851109Abstract: Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.Type: GrantFiled: March 31, 2008Date of Patent: December 14, 2010Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Frank E. Abboud, Henry Yun
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Publication number: 20090246644Abstract: Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Kishore K. Chakravorty, Frank E. Abboud, Henry Yun
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Patent number: 7535728Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 22, 2006Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Publication number: 20090098469Abstract: Design rules are described for a phase alternating shift mask for minimum chrome width and maximum segment length, where an embodiment employs during a cleaning process of the mask a megasonic power of 50 Watts at 1 MHz, and 30 Watts at 3 MHz. Some embodiments utilize an dry etch Carbon Tetrafluoride and Dioxygen based process. Other embodiments are described and claimed.Type: ApplicationFiled: October 12, 2007Publication date: April 16, 2009Inventors: Kishore K. Chakravorty, Sven Henrichs, Yi-Ping Liu, Henry Yun, Brian Irving, Alexander Tritchkov, Karmen Yung
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Patent number: 7418163Abstract: An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).Type: GrantFiled: March 28, 2002Date of Patent: August 26, 2008Inventors: Kishore K. Chakravorty, Joseph F. Ahadian, Johanna Swan, Thomas P. Thomas, Brandon C. Barnett, Ian Young
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Patent number: 7339798Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: September 8, 2005Date of Patent: March 4, 2008Assignee: Intel CorporationInventor: Kishore K. Chakravorty
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Patent number: 7120031Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: July 2, 2004Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 7112285Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.Type: GrantFiled: December 5, 2002Date of Patent: September 26, 2006Assignee: Intel CorporationInventor: Kishore K. Chakravorty
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Patent number: 7049704Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.Type: GrantFiled: May 6, 2004Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Johanna Swan, Brandon C. Barnett, Joseph F. Ahadian, Thomas P. Thomas, Ian Young
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Patent number: 6970362Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: July 31, 2000Date of Patent: November 29, 2005Assignee: Intel CorporationInventor: Kishore K. Chakravorty
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Patent number: 6963483Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.Type: GrantFiled: March 12, 2003Date of Patent: November 8, 2005Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Thomas S. Dory, C. Michael Garner
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Patent number: 6844663Abstract: A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.Type: GrantFiled: May 31, 2000Date of Patent: January 18, 2005Assignee: Candescent Intellectual PropertyInventors: Jueng Gil Lee, Christopher J. Spindt, Johan Knall, Matthew A. Bonn, Kishore K. Chakravorty
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Publication number: 20040238942Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: ApplicationFiled: July 2, 2004Publication date: December 2, 2004Applicant: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Publication number: 20040208416Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.Type: ApplicationFiled: May 6, 2004Publication date: October 21, 2004Applicant: INTEL CORPORATIONInventors: Kishore K. Chakravorty, Johanna Swan, Brandon C. Barnett, Joseph F. Ahadian, Thomas P. Thomas, Ian Young
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Patent number: 6775150Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 30, 2000Date of Patent: August 10, 2004Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 6764366Abstract: An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.Type: GrantFiled: October 31, 2001Date of Patent: July 20, 2004Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies CorporationInventors: Jueng Gil Lee, Christopher J. Spindt, Johan Knall, Matthew A. Bonn, Kishore K. Chakravorty
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Patent number: 6754407Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.Type: GrantFiled: May 30, 2002Date of Patent: June 22, 2004Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Johanna Swan, Brandon C. Barnett, Joseph F. Ahadian, Thomas P. Thomas, Ian Young
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Publication number: 20040110382Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Inventor: Kishore K. Chakravorty
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Patent number: 6710525Abstract: An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.Type: GrantFiled: October 19, 1999Date of Patent: March 23, 2004Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.Inventors: Jueng Gil Lee, Christopher J. Spindt, Johan Knall, Matthew A. Bonn, Kishore K. Chakravorty
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Publication number: 20030185484Abstract: An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).Type: ApplicationFiled: March 28, 2002Publication date: October 2, 2003Applicant: Intel CorporationInventors: Kishore K. Chakravorty, Joseph F. Ahadian, Johanna Swan, Thomas P. Thomas, Brandon C. Barnett, Ian Young