Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die can be coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic substrate. In one embodiment, the capacitor is formed of at least one high permittivity layer. In another embodiment, several high permittivity layers are interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.

Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.

Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens attached to it to facillitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a BGA package. The BGA package is bonded to the PCB using solder reflow technology.

Abstract: A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has optical waveguide structures in addition to electrical connections. An optically active device may be flip-bonded directly to an integrated circuit using solder bump technology. The integrated circuit then flip-bonded or wire-bonded to a BGA package. The package has alignment rails or balls and V-grooves to anchor the alignment rails/balls to align the BGA package to the PCB. The BGA package is bonded to the PCB using solder reflow technology.

Abstract: A thin film capacitor provides an interposer substrate between an integrated circuit die and an organic substrate. The interposer substrate includes a first conductive layer deposited on a base substrate layer. A portion of the first conductive layer provides a first electrode region serving as a first plate of the capacitor. Portions of a second conductive layer forming a second electrode region serving as a second plate of the capacitor. A dielectric layer is disposed between the first and second conductive layers to provide for capacitive regions between the first electrode region and the second electrode region. The base substrate layer and die may be based on similar semiconductor materials, such as Silicon or Gallium Arsenide, to provide an improved coefficient of thermal expansion match.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: Capacitors having defect isolation and bypass characteristics. The capacitors include a first electrode, a second electrode containing electrode segments, and a dielectric layer interposed between the first electrode and second electrode. The electrode segments of the second electrode are physically separated from other electrode segments. The capacitors further include an interconnection bus electrically coupling the electrode segments of the second electrode. Selective isolation of one or more electrode segments permits isolation and bypass of any defects identified in those electrode segments.

Abstract: A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a cathodic structure which is formed within an active area on a backplate. The cathodic structure includes a emitter electrode metal composed of strips of aluminum overlain by a layer of cladding material. The use of aluminum and cladding material to form emitter electrode metal gives emitter electrode metal segments which are highly conductive due to the high conductivity of aluminum. By using a suitable cladding material and processing steps, a bond between the aluminum and the cladding material is formed which has good electrical conductivity. In one embodiment, tantalum is used as a cladding material. Tantalum forms a bond with the overlying resistive layer which has good electrical conductivity. Thus, the resulting structure has very high electrical conductivity through the aluminum layer and high conductivity into the resistive layer.

Abstract: A structure and method for forming an column electrode for a field emission display device wherein the column electrode is disposed beneath the field emitters and the row electrode. In one embodiment, the present invention comprises depositing a resistor layer over portions of a column electrode. Next, an inter-metal dielectric layer is deposited over the column electrode. In the present embodiment, the inter-metal dielectric layer is deposited over portions of the resistor layer and over pad areas of the column electrode. After the deposition of the inter-metal dielectric layer, the column electrode is subjected to an anodization process such that exposed regions of the column electrode are anodized. In so doing, the present invention provides a column electrode structure which is resistant to column to row electrode shorts and which is protected from subsequent processing steps.

Abstract: A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material.

Abstract: A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips.

Abstract: A method for forming a gate electrode. In one embodiment, the present invention comprises depositing a gate metal over an underlying substrate such that a layer of the gate metal is formed above the underlying substrate. In the present invention, the layer of the gate metal is deposited to a thickness approximately the same as the thickness desired for the gate electrode. Next, the present invention deposits polymer particles onto the layer of gate metal. A hard mask layer is then deposited over the polymer particles and the layer of the gate metal. The present invention removes the polymer particles and portions of the hard mask layer which overlie the polymer particles such that first regions of the layer of the gate metal are exposed, and such that second regions of the layer of the gate metal remain covered by the hard mask layer.

Abstract: A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips.

Abstract: A structure and method for forming an anodized row electrode for a field emission display device. In one embodiment, the present invention comprises depositing a resistor layer over portions of a row electrode. Next, an inter-metal dielectric layer is deposited over the row electrode. In the present embodiment, the inter-metal dielectric layer deposited over portions of the resistor layer and over pad areas of the row electrode. After the deposition of the inter-metal dielectric layer, the row electrode is subjected to an anodization process such that exposed regions of the row electrode are anodized. In so doing, the present invention provides a row electrode structure which is resistant to row to column electrode shorts and which is protected from subsequent processing steps.

Abstract: An electron-emitting device contains a vertical emitter resistor patterned into multiple laterally separated sections (34, 34V, 46, or 46V) situated between the electron-emissive elements (40), on one hand, and emitter electrodes (32), on the other hand. Sections of the resistor are spaced apart along each emitter electrode.

Abstract: A method for selectively wet etching material during the formation of a field emission display device. In one embodiment, the selective wet etching method comprises immersing, in a fluid bath, a structure having a conductive row layer and a resistor layer. The structure further includes a pad area. In this embodiment, the fluid bath includes an organic-acid etchant. The present embodiment then applies a potential to the structure such that exposed regions of the resistor layer are selectively wet etched without significantly etching the conductive row layer or the pad area. In so doing, the present embodiment etches selected materials without requiring the use of highly toxic and hazardous conventional etchants.

Abstract: A method for uniformly depositing of polymer particles onto the surface of a gate metal during the formation of a gate electrode. In one embodiment, the present invention comprises immersing a substrate having a layer of a gate metal disposed over the surface thereof in a fluid bath containing polymer particles. In this embodiment, the fluid bath is contained within a fluid bath tank. Additionally, in the present embodiment, the layer of the gate metal disposed over the substrate has a thickness approximately the same as a desired thickness of the gate electrode to be formed. Next, the present embodiment applies a uniform potential across the surface of the layer of gate metal such that the polymer particles are uniformly deposited onto the layer of the gate metal. In so doing, the present embodiment uniformly deposits the polymer particles onto the layer of the gate metal.