Patents by Inventor Kiuchul Hwang

Kiuchul Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210367055
    Abstract: A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Robert E. Leoni, Nicholas J. Kolias
  • Publication number: 20210351288
    Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Christos Thomidis
  • Publication number: 20210320045
    Abstract: A semiconductor structure having: a crystalline substrate; a single crystalline semiconductor layer grown on the substrate; and a heat generating semiconductor device formed on a portion of the single crystalline layer. The substrate has an aperture in a selected portion thereof disposed in regions in the semiconductor layer under the heat generating device the aperture extending from a bottom portion of the substrate to the single crystalline semiconductor layer. Single crystalline or polycrystalline, thermal conductive material is disposed in the aperture, such material filling the aperture and extending from the bottom of the substrate, to and in direct contact with, the semiconductor layer.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 14, 2021
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Nicholas J. Kolias
  • Patent number: 11127596
    Abstract: A method includes providing a single crystal substrate having a buffer layer on a surface of the substrate. The buffer layer provides a transition between the crystallographic lattice structure of the substrate and the crystallographic lattice structure of the semiconductor layer and has its resistivity increased by ion implanting a dopant into the buffer layer; and forming semiconductor layer on the ion implanted buffer layer. The semiconductor layer may be a wide bandgap semiconductor layer having a high electron mobility transistors formed therein.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: September 21, 2021
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, Amanda Kerr
  • Patent number: 11101378
    Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Christos Thomidis
  • Publication number: 20210050216
    Abstract: A method includes providing a single crystal substrate having a buffer layer on a surface of the substrate. The buffer layer provides a transition between the crystallographic lattice structure of the substrate and the crystallographic lattice structure of the semiconductor layer and has its resistivity increased by ion implanting a dopant into the buffer layer; and forming semiconductor layer on the ion implanted buffer layer. The semiconductor layer may be a wide bandgap semiconductor layer having a high electron mobility transistors formed therein.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 18, 2021
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, Amanda Kerr
  • Publication number: 20200328296
    Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Christos Thomidis
  • Patent number: 10797129
    Abstract: A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 6, 2020
    Inventor: Kiuchul Hwang
  • Patent number: 10541148
    Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 21, 2020
    Assignee: Raytheon Company
    Inventors: Kezia Cheng, Kamal Tabatabaie Alavi, Adrian D. Williams, Christopher J. MacDonald, Kiuchul Hwang
  • Publication number: 20190198346
    Abstract: A stack of layers providing an ohmic contact with the semiconductor, a lower metal layer of the stack is disposed in direct contact with the semiconductor; and a radiation absorption control layer disposed over the lower layer for controlling an amount of the radiant energy to be absorbed in the radiation absorption control layer during exposure of the stack to the radiation during a process used to alloy the stack with the semiconductor to form the ohmic contact.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 27, 2019
    Applicant: Raytheon Company
    Inventors: Kezia Cheng, Kamal Tabatabaie Alavi, Adrian D. Williams, Christopher J. MacDonald, Kiuchul Hwang
  • Patent number: 10134839
    Abstract: A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: November 20, 2018
    Assignee: RAYTHEON COMPANY
    Inventor: Kiuchul Hwang
  • Publication number: 20180286947
    Abstract: A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: Raytheon Company
    Inventor: Kiuchul Hwang
  • Patent number: 9887089
    Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 6, 2018
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Dale M. Shaw, Adrian D. Williams
  • Publication number: 20180019298
    Abstract: A structure having: a substrate; a passivation layer disposed over a surface of substrate; an etch stop layer disposed on the passivation layer; resistor comprising tantalum nitride, disposed on the etch stop layer. The etch stop layer has an etch rate at least 100 times slower than an etch rate of the tantalum nitride to a predetermined etchant.
    Type: Application
    Filed: July 18, 2016
    Publication date: January 18, 2018
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Robert T. Soter, Bruce Leblanc, Adrian D. Williams
  • Publication number: 20170025278
    Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid dielectric, such as air.
    Type: Application
    Filed: October 5, 2016
    Publication date: January 26, 2017
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Dale M. Shaw, Adrian D. Williams
  • Publication number: 20160329420
    Abstract: A Field Effect Transistor structure is provided having: a semi-insulating substrate; a semiconductor mesa structure disposed on the substrate and having a notch in an outer sidewall of the mesa structure; a source electrode disposed within the opposing sidewalls in ohmic contact with a source region of the mesa structure; a drain electrode disposed within the opposing sidewalls in ohmic contact with a drain region of the mesa; and a gate electrode, having an inner portion disposed between, and laterally of, the source electrode and the drain electrode and in Schottky contact with the mesa structure, extending longitudinally towards the notch and having outer portions extending beyond the mesa structure and over portions of the substrate outside of the mesa structure. In one embodiment, the mesa structure includes a pair of notches projecting inwardly towards each other and the inner portion of the gate extends longitudinally between the pair of notches.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 10, 2016
    Applicant: RAYTHEON COMPANY
    Inventor: Kiuchul Hwang
  • Publication number: 20150235856
    Abstract: A semiconductor structure having a T-shaped electrode. The electrode has a top portion and a narrower stem portion extending from the top portion to a surface of a substrate. A solid dielectric layer has side portions juxtaposed and abutting sidewalls of a lower portion of the stem of electrode. A bottom surface of the top portion is spaced from an upper surface portion by a non-solid, dielectric, such as air.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, Dale M. Shaw, Adrian D. Williams
  • Publication number: 20120273852
    Abstract: A semiconductor structure having: a semiconductor comprising a indium gallium phosphide and molybdenum metal in Schottky contact with the semiconductor.
    Type: Application
    Filed: July 9, 2012
    Publication date: November 1, 2012
    Applicant: Raytheon Company
    Inventor: Kiuchul Hwang
  • Publication number: 20110053336
    Abstract: A method for forming a capacitor and a transistor device on different surface portions of a semiconductor structure includes forming a passivation dielectric layer for the device; forming a bottom electrode for the capacitor; forming a removable layer extending over the bottom electrode and over the passivation dielectric layer with a window therein, such window exposing said bottom electrode; depositing a capacitor dielectric layer of the same or different material as the passivation dielectric layer over the removable layer with first portions passing through the window onto the exposed bottom electrode and second portions being over the removable layer, the thickness of the deposited layer being different from the thickness of the passivation layer; removing the removable layer with the second portions thereon while leaving said first portions on the bottom electrode; and forming a top electrode for the capacitor on the second portions remaining on the bottom electrode.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 3, 2011
    Applicant: Raytheon Company
    Inventors: Kiuchul Hwang, David W. Bennett, Huy Q. Nguyen
  • Publication number: 20100244105
    Abstract: A semiconductor structure having: a semiconductor comprising a indium gallium phosphide and molybdenum metal in Schottky contact with the semiconductor.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventor: Kiuchul Hwang