Patents by Inventor Kiwamu Adachi
Kiwamu Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230125605Abstract: Provided is a semiconductor device capable of maintaining the flatness of a glass substrate and sufficiently protecting an end portion of the glass substrate. A semiconductor device according to one aspect of the present disclosure includes: a glass substrate including a first surface, a second surface opposite to the first surface, and a first side surface between the first surface and the second surface; wirings provided on the first and second surfaces; a first insulating film that covers the first surface; a second insulating film that covers the second surface; and a third insulating film that covers the first side surface, the third insulating film being continuous with at least one of the first and second insulating films.Type: ApplicationFiled: March 23, 2021Publication date: April 27, 2023Inventors: YUTO TANAKA, SHUICHI OKA, SHUN MITARAI, KIWAMU ADACHI, TAKAHIRO IGARASHI, HIIZU OHTORII, NAOKI KAKOIYAMA, KOUSUKE SEKI, HIROYUKI SHIGETA
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Publication number: 20220234126Abstract: A method of manufacturing a mounting substrate, the method includes: transferring part or all of a plurality of devices on a device substrate onto a wiring substrate, and temporarily fixing the transferred devices to the wiring substrate with use of a fixing layer having viscosity, the device substrate including a support substrate and the plurality of devices fixed on the support substrate; and performing a reflow process on the wiring substrate to electrically connect the transferred devices with the wiring substrate, and thereby forming the mounting substrate.Type: ApplicationFiled: April 15, 2022Publication date: July 28, 2022Inventors: Hiizu OOTORII, Kiwamu ADACHI, Takeshi MIZUNO
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Patent number: 11370047Abstract: A method of manufacturing a mounting substrate, the method includes: transferring part or all of a plurality of devices on a device substrate onto a wiring substrate, and temporarily fixing the transferred devices to the wiring substrate with use of a fixing layer having viscosity, the device substrate including a support substrate and the plurality of devices fixed on the support substrate; and performing a reflow process on the wiring substrate to electrically connect the transferred devices with the wiring substrate, and thereby forming the mounting substrate.Type: GrantFiled: May 6, 2014Date of Patent: June 28, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Hiizu Ootorii, Kiwamu Adachi, Takeshi Mizuno
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Publication number: 20220102230Abstract: Provided is a protection structure that appropriately protects a side surface of a glass substrate in a semiconductor module. A semiconductor module is provided with a glass substrate. The glass substrate is provided with a plurality of straight line portions and a corner portion interposed between the straight line portions on a side surface thereof. A protective material is formed on at least a part of the side surface of the glass substrate. The corner portion of the glass substrate is located on an inner side of a straight line connecting ridges of protective materials formed on the straight line portions (a center side of the glass substrate). Therefore, the corner portion is protected against an impact on the side surface of the glass substrate.Type: ApplicationFiled: November 25, 2019Publication date: March 31, 2022Inventors: HIIZU OHTORII, KIWAMU ADACHI, NAOKI KAKOIYAMA
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Patent number: 10483413Abstract: A photoelectric module of the present disclosure includes an optical device including an optical function element array made of a first base material, and a plurality of light emitting/receiving elements made of a second base material, wherein the optical function element array includes an optical substrate and a plurality of optical function elements, the optical substrate having a first surface and a second surface, and the optical function elements being integrated with the optical substrate and being arranged one-dimensionally or two-dimensionally, and the light emitting/receiving elements and their respective optical function elements face each other with the optical substrate in between to be located on a same axis in a direction perpendicular to the optical substrate, and the light emitting/receiving elements are disposed on the second surface with a space in between while being separated in units of a smaller number than array number in the optical function element array.Type: GrantFiled: April 23, 2015Date of Patent: November 19, 2019Assignee: Sony CorporationInventors: Hiizu Ootorii, Kazunao Oniki, Koki Uchino, Hideyuki Suzuki, Hiroshi Ozaki, Kazuki Sano, Eiji Otani, Shinji Rokuhara, Kiwamu Adachi, Shuichi Oka, Shusaku Yanagawa, Hiroshi Morita, Takeshi Ogura
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Publication number: 20190103501Abstract: A light-receiving device of an embodiment of the present disclosure includes, on a first principal surface of a semiconductor layer, a pixel region that includes a plurality of light-receiving pixels each receiving light incident from side of a second principal surface of the semiconductor layer. The light-receiving device further includes, throughout a gap between the second principal surface and the pixel region, a low-impurity region having a relatively lower impurity concentration than the pixel region. The light-receiving pixels each include one or a plurality of photoelectric current extraction regions each including, on the first principal surface, an anode region and a cathode region, and a circuit region that is electrically coupled to each of the cathode regions and is electrically separated from the impurity region.Type: ApplicationFiled: February 15, 2017Publication date: April 4, 2019Applicant: SONY CORPORATIONInventors: Takahiro IGARASHI, Takahiro SONODA, Atsushi SUZUKI, Shinya YAMAKAWA, Hiroshi YUMOTO, Izuho HATADA, Takeshi KODAMA, Kiwamu ADACHI, Katsuji MATSUMOTO
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Patent number: 10134662Abstract: A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.Type: GrantFiled: September 8, 2015Date of Patent: November 20, 2018Assignee: Sony CorporationInventors: Kiwamu Adachi, Katsuji Matsumoto, Takeshi Kodama, Shuichi Oka, Hiizu Ootorii, Kazunari Saitou, Kei Satou
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Patent number: 9929199Abstract: There is provided a radiation detector including: a plurality of photoelectric conversion devices, each photoelectric conversion device formed at least partially within an embedding layer and having a light receiving surface situated at least partially outside of the embedding layer, and a plurality of scintillator crystals, at least a first scintillator crystal of the plurality of scintillator crystals in contact with at least one light receiving surface at a proximal end, wherein a cross-section of the first scintillator crystal at the proximal end is smaller than a cross-section of the first scintillator crystal at a distal end.Type: GrantFiled: August 21, 2014Date of Patent: March 27, 2018Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takahiro Igarashi, Izuho Hatada, Takeshi Kodama, Kiwamu Adachi, Shuichi Oka, Shun Mitarai, Hiizu Ootorii, Shusaku Yanagawa, Katsuji Matsumoto
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Publication number: 20170287823Abstract: A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a plurality of electrodes on a semiconductor layer, and thereafter forming one of solder bumps at a position facing each of the electrodes; (2) a step of covering the solder bumps with a coating layer, and thereafter selectively etching the semiconductor layer with use of the coating layer as a mask to separate the semiconductor layer into a plurality of elements; and (3) a step of removing the coating layer, and thereafter mounting the elements on a wiring substrate to direct the solder bumps toward the wiring substrate, thereby forming the mounting substrate.Type: ApplicationFiled: September 8, 2015Publication date: October 5, 2017Applicant: Sony CorporationInventors: Kiwamu Adachi, Katsuji Matsumoto, Takeshi Kodama, Shuichi Oka, Hiizu Ootorii, Kazunari Saitou, Kei Satou
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Patent number: 9771305Abstract: A sintering apparatus includes: a non-transportable section mounted in the atmosphere; a transportable section that has a mold capable of accommodating a material to be processed and is loaded detachably with respect to the non-transportable section; and a covering member that envelops the transportable section loaded on the non-transportable section in an almost hermetically sealed state and allows the transportable section to be separated from the non-transportable section with the transportable section enveloped in the almost hermetically sealed state.Type: GrantFiled: June 3, 2014Date of Patent: September 26, 2017Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kiwamu Adachi
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Publication number: 20170170339Abstract: A photoelectric module of the present disclosure includes an optical device including an optical function element array made of a first base material, and a plurality of light emitting/receiving elements made of a second base material, wherein the optical function element array includes an optical substrate and a plurality of optical function elements, the optical substrate having a first surface and a second surface, and the optical function elements being integrated with the optical substrate and being arranged one-dimensionally or two-dimensionally, and the light emitting/receiving elements and their respective optical function elements face each other with the optical substrate in between to be located on a same axis in a direction perpendicular to the optical substrate, and the light emitting/receiving elements are disposed on the second surface with a space in between while being separated in units of a smaller number than array number in the optical function element array.Type: ApplicationFiled: April 23, 2015Publication date: June 15, 2017Inventors: Hiizu OOTORII, Kazunao ONIKI, Koki UCHINO, Hideyuki SUZUKI, Hiroshi OZAKI, Kazuki SANO, Eiji OTANI, Shinji ROKUHARA, Kiwamu ADACHI, Shuichi OKA, Shusaku YANAGAWA, Hiroshi MORITA, Takeshi OGURA
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Patent number: 9672983Abstract: A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.Type: GrantFiled: May 25, 2012Date of Patent: June 6, 2017Assignee: SONY CORPORATIONInventors: Shuichi Oka, Shusaku Yanagawa, Kiwamu Adachi
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Publication number: 20160163754Abstract: There is provided a radiation detector including: a plurality of photoelectric conversion devices, each photoelectric conversion device formed at least partially within an embedding layer and having a light receiving surface situated at least partially outside of the embedding layer, and a plurality of scintillator crystals, at least a first scintillator crystal of the plurality of scintillator crystals in contact with at least one light receiving surface at a proximal end, wherein a cross-section of the first scintillator crystal at the proximal end is smaller than a cross-section of the first scintillator crystal at a distal end.Type: ApplicationFiled: August 21, 2014Publication date: June 9, 2016Inventors: Takahiro Igarashi, Izuho Hatada, Takeshi Kodama, Kiwamu Adachi, Shuichi Oka, Shun Mitarai, Hiizu Ootoril, Shusaku Yanagawa, Katsuji Matsumoto
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Publication number: 20150047971Abstract: A sputtering target includes a conductive barium titanate sintered material with generation density of crystal grain aggregate (12) having a grain diameter of 10 ?m or more on a cleavage surface of less than 0.2 piece/cm2.Type: ApplicationFiled: February 25, 2013Publication date: February 19, 2015Applicant: Sony CorporationInventors: Kiwamu Adachi, Shusaku Yanagawa
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Publication number: 20140367251Abstract: A sintering apparatus includes: a non-transportable section mounted in the atmosphere; a transportable section that has a mold capable of accommodating a material to be processed and is loaded detachably with respect to the non-transportable section; and a covering member that envelops the transportable section loaded on the non-transportable section in an almost hermetically sealed state and allows the transportable section to be separated from the non-transportable section with the transportable section enveloped in the almost hermetically sealed state.Type: ApplicationFiled: June 3, 2014Publication date: December 18, 2014Applicant: Sony CorporationInventor: Kiwamu Adachi
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Publication number: 20140339289Abstract: A method of manufacturing a mounting substrate, the method includes: transferring part or all of a plurality of devices on a device substrate onto a wiring substrate, and temporarily fixing the transferred devices to the wiring substrate with use of a fixing layer having viscosity, the device substrate including a support substrate and the plurality of devices fixed on the support substrate; and performing a reflow process on the wiring substrate to electrically connect the transferred devices with the wiring substrate, and thereby forming the mounting substrate.Type: ApplicationFiled: May 6, 2014Publication date: November 20, 2014Applicant: Sony CorporationInventors: Hiizu OOTORII, Kiwamu ADACHI, Takeshi MIZUNO
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Patent number: 8536463Abstract: A method for manufacturing a printed-circuit board including: a capacitive element forming step of embedding a capacitive element in a substrate resin layer inside a substrate that includes a plurality of wiring layers laminated with the substrate resin layer interposed in between, the capacitive element forming step including forming a lower electrode using a conductive layer on one of the plurality of wiring layers, or using one of the plurality of wiring layers; forming a crystalline metal oxide-containing capacitor dielectric film at a temperature at or below a heat-resistant temperature of the substrate resin layer, and at or above room temperature; and forming an upper electrode on an upper surface of the capacitor dielectric film on the side opposite to the lower electrode.Type: GrantFiled: October 20, 2010Date of Patent: September 17, 2013Assignee: Sony CorporationInventors: Mitsuharu Shoji, Kiwamu Adachi
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Publication number: 20120307469Abstract: A multilayer wiring board includes: a functional area which includes a thin film capacitor having a dielectric layer between an upper electrode and a lower electrode; and a peripheral area other than the functional area, wherein a mooring portion in which the dielectric layer and a conductive layer are laminated is provided in at least a portion of the peripheral area, and a roughness of a surface of the conductive layer which contacts the dielectric layer is greater than a roughness of a surface of the upper electrode or the lower electrode which contacts the dielectric layer.Type: ApplicationFiled: May 25, 2012Publication date: December 6, 2012Applicant: SONY CORPORATIONInventors: Shuichi Oka, Shusaku Yanagawa, Kiwamu Adachi
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Publication number: 20120200797Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: SONY CORPORATIONInventors: Kiwamu ADACHI, Satoshi HORIUCHI
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Patent number: 8237242Abstract: A capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially stacked. The dielectric layer has a stacked layer structure including a predetermined number of hafnium oxide sublayers and predetermined number of tantalum oxide sublayers. The number, materials, and thicknesses of the sublayers are determined so that the thickness ratio has a range in which, in voltage-leakage current characteristics showing the relationship between the voltage between the first and second electrodes and the leakage current, a start voltage at which the slope of an increase in the current starts to discontinuously increase satisfies an electric field strength of 3 [MV/cm] or more when the ratio of the total thickness of the predetermined number of tantalum oxide sublayers to the total thickness of the dielectric layer is varied, and the thickness ratio is within the range such that the start voltage is within the range.Type: GrantFiled: July 23, 2007Date of Patent: August 7, 2012Assignee: Sony CorporationInventors: Kiwamu Adachi, Satoshi Horiuchi