Patents by Inventor Kiwamu Watanabe

Kiwamu Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8155204
    Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiro Suzumura, Shuji Michinaka, Kiwamu Watanabe, Masashi Jobashi, Takaya Ogawa, Hiromitsu Nakayama, Satoshi Takekawa, Yoshinori Shigeta, Akihiro Oue
  • Patent number: 8023565
    Abstract: A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiro Suzumura, Akihiro Oue, Kunihiko Yahagi, Shuji Michinaka, Satoshi Takekawa, Kiwamu Watanabe
  • Publication number: 20110129371
    Abstract: A closed type compressor of a low overall height and small vibrations provided with a structure comprising a balancing weight (142) formed of a first balancing weight (146) and a second balancing weight (148) and fixed to eccentric shaft portion (112), the first balancing weight (146) located closer to a main shaft portion (109) than the second balancing weight (148), and the second balancing weight (148) jutting out to a position further from an axis of the eccentric shaft portion (112) than the first balancing weight (146).
    Type: Application
    Filed: July 21, 2009
    Publication date: June 2, 2011
    Inventor: Kiwamu Watanabe
  • Publication number: 20100200290
    Abstract: Including a storage box for accommodating a printed circuit board having a heat sink, an aluminum plate for closing an opening part of the storage box, and a rubber bush for supporting the printed circuit board from an opposite side of the opening part, the heat sink and the aluminum plate are brought to contact with each other by way of the insulating sheet, so that the heat of the heat sink may be transmitted to the aluminum plate, and released.
    Type: Application
    Filed: February 3, 2010
    Publication date: August 12, 2010
    Applicant: Panasonic Corporation
    Inventors: Shigetomi TOKUNAGA, Kiwamu WATANABE
  • Publication number: 20100200095
    Abstract: The inclination of the suction reed at the time of sucking the refrigerant can be increased when L/S is not more than 0.25 where S (mm2) represents the area within the periphery of the suction valve seat of the suction reed, and L (mm) represents the length between the support end and the tip on the opening/closing part side of the suction reed. The increased inclination of the suction reed smoothes the flow of the refrigerant into the cylinder bore from the inside of the suction valve seat so as to reduce the suction resistance and the clearance volume, thereby reducing the re-expansion loss. As a result, the refrigerant flow is increased to increase the volumetric efficiency, thereby improving the freezing performance of the hermetic compressor.
    Type: Application
    Filed: April 13, 2007
    Publication date: August 12, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazuhiro Yokota, Kiwamu Watanabe
  • Publication number: 20100158721
    Abstract: Provided is a hermetic compressor in which an electric element having a stator and rotor provided therein and a compression element driven by the electric element are housed and the compression element includes a shaft which has a main shaft portion and an eccentric shaft portion, a cylinder block, a main shaft bearing which is formed in the cylinder block and supports the main shaft bearing of the shaft, a piston which reciprocates, a connection mechanism which connects the piston to the eccentric shaft portion, and a thrust-ball bearing, the thrust ball bearing having a plurality balls and a holder portion for holding the balls, and the holder portion being formed of polymer obtained by polycondensating diaminobutane and adipic acid.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 24, 2010
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Seigo Yanase, Akihiko Kubota, Atsushi Naruse, Kiwamu Watanabe, Hironari Akashi, Yoichiro Nakamura
  • Patent number: 7686592
    Abstract: A suction muffler receives low-temperature refrigerant gas discharged into a hermetic container from a suction pipe by a gas catcher, and feeds the gas to a compressor. The lower end of an opening of the gas catcher is located at a position lower than the lower end of an orifice of the suction pipe so as to catch the refrigerant gas falling obliquely downward inside the hermetic container.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: March 30, 2010
    Assignee: Panasonic Corporation
    Inventors: Akira Inoue, Seigo Yanase, Kiwamu Watanabe, Hidenori Kobayashi
  • Publication number: 20100047093
    Abstract: A compressor has a hermetic container filled with a lubricant and accommodates an electric element provided with a stator and a rotor and a compressing element, wherein the compressing element includes a shaft, a cylinder block, a piston, a connection mechanism, a bearing, and a thrust ball bearing provided between the rotor and a bearing end surface as an end surface of the bearing, and wherein the thrust ball bearing includes a plurality of balls, a holder portion for holding the balls, upper and lower races disposed on and beneath the balls, a rotation regulation portion for regulating a rotation of the lower race, and a thrust surface provided at the bearing end surface so as to contact with a lower surface of the lower race.
    Type: Application
    Filed: October 8, 2008
    Publication date: February 25, 2010
    Applicant: Panasonic Corporation
    Inventor: Kiwamu Watanabe
  • Patent number: 7602319
    Abstract: An image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix, a suffix, and a syntax; a variable length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length, and, by using data contained in the bit stream and the suffix length, simultaneously decode the prefix and the suffix and output the result if the syntax selection signal selects the prefix 1 and the suffix, and decode the syntax and output the result if the syntax selection signal selects the syntax; a level formation device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix, the decoded suffix, and the decoded syntax, and update the suffix length.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: October 13, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiro Suzumura, Shuji Michinaka, Kiwamu Watanabe, Satoshi Takekawa, Masashi Jobashi, Hiromitsu Nakayama, Yoshinori Shigeta, Takaya Ogawa, Akihiro Oue
  • Publication number: 20090245351
    Abstract: A motion vector decoding section alternately decodes motion vectors of sub-reference blocks that respectively belong to two reference blocks in different reference directions. Upon decoding of each set of motion vectors of the sub-reference blocks in the two reference blocks, a block boundary strength calculating section calculates a block boundary strength bS of a sub-macroblock currently being processed and corresponding to the position of the sub-reference blocks.
    Type: Application
    Filed: March 16, 2009
    Publication date: October 1, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kiwamu Watanabe
  • Patent number: 7586426
    Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: September 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Watanabe, Shuji Michinaka, Tatsuhiro Suzumura, Hiromitsu Nakayama, Yoshinori Shigeta, Satoshi Takekawa, Masashi Jobashi, Takaya Ogawa, Akihiro Oue
  • Patent number: 7567189
    Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: July 28, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaya Ogawa, Masashi Jobashi, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka
  • Publication number: 20090136369
    Abstract: This hermetic compressor includes a regulation mechanism, which is arranged between a lower washer and an upper end face of a bearing, for regulating a movable distance in a thrust direction of the lower washer so that the movable distance can be shorter than clearance between an inner diameter of the lower washer and an outer diameter of a main shaft portion. It is possible to prevent the inner diameter of the lower washer from coming into contact with the outer diameter of the main shaft portion by this regulation mechanism.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 28, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takashi Kakiuchi, Kiwamu Watanabe
  • Publication number: 20090104050
    Abstract: A suction muffler receives low-temperature refrigerant gas discharged into a hermetic container from a suction pipe by a gas catcher, and feeds the gas to a compressor. The lower end of an opening of the gas catcher is located at a position lower than the lower end of an orifice of the suction pipe so as to catch the refrigerant gas falling obliquely downward inside the hermetic container.
    Type: Application
    Filed: November 21, 2005
    Publication date: April 23, 2009
    Inventors: Akira Inoue, Seigo Yanase, Kiwamu Watanabe, Hidenori Kobayashi
  • Publication number: 20090097567
    Abstract: An encoding apparatus includes: an orthogonal transformation unit configured to orthogonally transform image data of a predetermined block size; a binarization unit configured to binarize the image data outputted from the orthogonal transformation unit; an arithmetic encoding unit configured to arithmetically encode the binary data generated by the binarization unit; and a prediction unit configured to predict, from the binary data, whether or not the amount of arithmetically encoded data generated by the arithmetic encoding unit exceeds a permissible maximum code amount based on a predetermined encoding standard. The encoding apparatus performs, when the prediction result is that the amount of arithmetically encoded data exceeds the maximum code amount, control to prevent the arithmetic encoding by the arithmetic encoding unit from being performed to the binary data corresponding to the prediction result.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshinori Shigeta, Hiromitsu Nakayama, Kiwamu Watanabe, Satoshi Takekawa, Tatsuhiro Suzumura, Takaya Ogawa, Masashi Jobashi
  • Publication number: 20080291062
    Abstract: An image coding apparatus includes a variable length coding section, an arithmetic coding section and a common buffer memory. The variable length coding section inputs image data and outputs a binarized code sequence applied with variable length coding. The arithmetic coding section applies arithmetic coding to the binarized code sequence outputted from the variable length coding section. The common buffer memory transmits and receives data between the variable length coding section and the arithmetic coding section.
    Type: Application
    Filed: May 20, 2008
    Publication date: November 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiwamu Watanabe, Shuji Michinaka, Tatsuhiro Suzumura, Hiromitsu Nakayama, Yoshinori Shigeta, Satoshi Takekawa, Masashi Jobashi, Takaya Ogawa, Akihiro Oue
  • Publication number: 20080238733
    Abstract: According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to recei
    Type: Application
    Filed: March 3, 2008
    Publication date: October 2, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuhiro SUZUMURA, Shuji Michinaka, Kiwamu Watanabe, Satoshi Takekawa, Masashi Jobashi, Hiromitsu Nakayama, Yoshinori Shigeta, Takaya Ogawa, Akihiro Oue
  • Publication number: 20080198046
    Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 21, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takaya OGAWA, Masashi Jobashi, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka
  • Publication number: 20080137754
    Abstract: The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.
    Type: Application
    Filed: September 19, 2007
    Publication date: June 12, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiro SUZUMURA, Shuji Michinaka, Kiwamu Watanabe, Masashi Jobashi, Takaya Ogawa, Hiromitsu Nakayama, Satoshi Takekawa, Yoshinori Shigeta, Akihiro Oue
  • Publication number: 20070147511
    Abstract: An image processing apparatus includes: a frame memory; a buffer memory that stores pixel values of macroblocks of a first region including a first macroblock; a deblocking filter unit that is operable to: (1) read out the pixel values of the first region from the buffer memory; (2) apply the deblocking filter to the first macroblock; and (3) store the pixel values back into the buffer memory; and a pixel transfer unit that is operable to: (4) transfer pixel values of a macroblock not included in a second region that includes a second macroblock to be processed next to the first macroblock, from the buffer memory to the frame memory; and (5) transfer pixel values of a macroblock included in the second region but not included in the first region, from the frame memory to the buffer memory.
    Type: Application
    Filed: December 18, 2006
    Publication date: June 28, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaya Ogawa, Kiwamu Watanabe, Tatsuhiro Suzumura, Satoshi Takekawa, Hiromitsu Nakayama, Yoshinori Shigeta, Akihiro Oue, Shuji Michinaka