Patents by Inventor Kiyofumi Abe

Kiyofumi Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146925
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: performs a first transform on a residual signal of the current block using a first transform basis to generate first transform coefficients; and performs a second transform on the first transform coefficients using a second transform basis to generate second transform coefficients and quantizes the second transform coefficients, when the first transform basis is the same as a predetermined transform basis; and quantizes the first transform coefficients without performing the second transform, when the first transform basis is different from the predetermined transform basis.
    Type: Application
    Filed: December 20, 2023
    Publication date: May 2, 2024
    Inventors: Masato OHKAWA, Hideo SAITOU, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH
  • Publication number: 20240146968
    Abstract: An encoder that encodes a moving picture using an inter prediction process, and includes circuitry and memory coupled to the circuitry. In the inter prediction process, when performing a correction process which is a local illumination compensation (LIC) process for a prediction image, the circuitry, in operation; performs the correction process on a prediction image generated using a finally-derived motion vector that is finally derived in a stage before the correction process; and after the correction process, determines, as a final prediction image, the prediction image subjected to the correction process, without applying other correction process on the prediction image.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Publication number: 20240146947
    Abstract: An encoder includes circuitry and memory. The circuitry determines whether a first virtual pipeline decoding unit (VPDU) is split into smaller blocks and whether a second VPDU is split into smaller blocks. In response to a determination the first VPDU is not split into smaller blocks and a determination the second VPDU is split into smaller blocks, a block of chroma samples is predicted without using luma samples. In response to a determination the first VPDU is split into smaller blocks and a determination the second VPDU is split into smaller blocks, the block of chroma samples is predicted using luma samples. In response to a determination the first VPDU is not split into smaller blocks and a determination the second VPDU is not split into smaller block, the block of chroma samples is predicted using luma samples. The block is encoded using the predicted chroma samples.
    Type: Application
    Filed: January 3, 2024
    Publication date: May 2, 2024
    Inventors: Che-Wei KUO, Jing Ya LI, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Rohith MARS, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Patent number: 11971546
    Abstract: An image encoder performs a first partitioning including using a first partition mode, without writing first splitting information indicative of the first partition mode into a bitstream, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition; and performs a second partitioning on the second block by writing second splitting information indicative of a second partition mode into the bitstream, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in certain conditions.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: April 30, 2024
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Ryuichi Kanoh, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 11973932
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: determines whether an image format of a video is a format including a chroma component; when it is determined that the image format is a format including a chroma component, signals a flag indicating whether application of JCCR is allowed or not in a header of a stream, and (i) encodes the video with application of the JCCR allowed, or (ii) encodes the video with application of the JCCR not allowed; and when it is determined that the image format is a format including no chroma component, signals no flag indicating whether application of the JCCR is allowed or not in the header of the stream, and encodes the video with application of the JCCR not allowed.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 30, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Publication number: 20240137514
    Abstract: An encoder includes circuitry and memory. In both of a first type of residual coding where an orthogonal transform is applied and a second type of residual coding where the orthogonal transform is skipped, wherein when a restriction on a number of CABAC processes allows CABAC coding of a set of coefficient information flags, the circuitry: encodes the coefficient information flags by CABAC; and otherwise, the circuitry: skips the CABAC encoding of the coefficient information flags; and the circuitry encodes a remainder value of the coefficient with Golomb-Rice code when the coefficient information flags are encoded; and otherwise the circuitry encodes a value of the coefficient with the Golomb-Rice code, wherein in the second type of residual coding, the circuitry encodes absolute value flags each relating to an absolute value of the coefficient after encoding the coefficient information flags and before encoding the remainder value of the coefficient.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Yusuke KATO, Takahiro NISHI, Tadamasa TOMA, Kiyofumi ABE
  • Publication number: 20240137521
    Abstract: An encoding method of generating a first bitstream to be merged with a second bitstream. The encoding method includes: determining a first adaptive loop filter (ALF) setting that is a setting of an ALF for a first subpicture to be encoded into the first bitstream; encoding first ALF setting information indicating the first ALF setting into the first bitstream; and encoding the first subpicture into the first bitstream according to the first ALF setting, in which, in the determining of the first ALF setting, an ALF setting that does not refer to an adaption parameter set (APS) index referred to in the second bitstream is determined as the first ALF setting.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 25, 2024
    Inventors: Virginie Drugeon, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 11968378
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives a correction parameter using only a neighboring reconstructed image that neighbors a processing unit which has a determined size and is located at an upper left of a current block to be processed in an image, among neighboring reconstructed images that neighbor the current block, and performs correction processing of the current block based on the correction parameter derived, when the current block has a size larger than the determined size.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 23, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Publication number: 20240129523
    Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 18, 2024
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20240129516
    Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Inventors: Takashi HASHIMOTO, Takahiro NISHI, Tadamasa TOMA, Kiyofumi ABE, Ryuichi KANOH
  • Publication number: 20240121384
    Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.
    Type: Application
    Filed: December 14, 2023
    Publication date: April 11, 2024
    Inventors: Jing Ya LI, Ru Ling Liao, Chong Soon Lim, Han Boon Teo, Hai Wei Sun, Che Wei Kuo, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 11956466
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 11956434
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, for each coefficient of a plurality of coefficients included in a block, determines a base level relating to Context-Based Adaptive Binary Arithmetic Coding (CABAC) for the coefficient, and encodes an absolute value of the coefficient. In determining the base level, when one or more flags are used in encoding the absolute value of the coefficient, the base level is determined to be a first value, and when one or more flags are not used in the encoding, the base level is determined to be a second value that is smaller than the first value. In encoding the absolute value of the coefficient, when one or more flags are not used, a rice parameter is determined based on the base level which is equal to the second value, and the coefficient is binarized using the rice parameter.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: April 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yusuke Kato, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 11956467
    Abstract: An encoder, when sub-block encoding is to be performed, determines a plurality of sub-blocks in a first image block, the plurality of sub-blocks including a first sub-block, determines a first motion vector for the first sub-block by referring to a first candidate list, performs first inter prediction processing on the first sub-block using the first motion vector, and encodes the first image block using a result of the first inter prediction processing. When partition encoding is to be performed, the encoder, in operation, determines a plurality of partitions in a second image block, the plurality of partitions including a first partition, determines a second motion vector for the first partition by referring to a second candidate list, performs second inter prediction processing on the first partition using the second motion vector, and encodes the second image block using a result of the second inter prediction processing.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: April 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Publication number: 20240114137
    Abstract: An encoder that encodes a video includes a processor and memory. Using the memory, the processor: derives a prediction error of an image included in the video, by subtracting a prediction image of the image from the image; determines a secondary transform basis based on a primary transform basis, the primary transform basis being a transform basis for a primary transform to be performed on the prediction error, the secondary transform basis being a transform basis for a secondary transform to be performed on a result of the primary transform; performs the primary transform on the prediction error using the primary transform basis; performs the secondary transform on a result of the primary transform using the secondary transform basis; performs quantization on a result of the secondary transform; and encodes a result of the quantization as data of the image.
    Type: Application
    Filed: November 29, 2023
    Publication date: April 4, 2024
    Inventors: Ryuichi KANOH, Tadamasa TOMA, Kiyofumi ABE, Takahiro NISHI
  • Publication number: 20240114169
    Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Jing Ya LI, Che Wei KUO, Chong Soon LIM, Chu Tong WANG, Han Boon TEO, Hai Wei SUN, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Yusuke KATO
  • Publication number: 20240114160
    Abstract: An image decoder includes circuitry and a memory, wherein the circuitry, in operation, calculates first values of a first partition in a current block, using a first motion vector for the first partition; calculates second values of a second partition in the current block, using a second motion vector for the second partition; calculates third values of a set of pixels between the first partition and the second partition, using the first motion vector; calculates fourth values of the set of pixels, using the second motion vector; and weights the third values and the fourth values. A number of pixels in a row in the set of pixels is two or more, and two or more weights applied to the third values increase along the row.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20240114134
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20240114129
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Jing Ya LI, Chong Soon Lim, Han Boon Teo, Che Wei Kuo, Hai Wei Sun, Chu Tong Wang, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Patent number: 11949884
    Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: April 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li