Abstract: According to the insulated gate transistor, a gate electrode (11A) is provided on a main surface of a glass substrate (2); a first part of an insulating layer (gate insulating layer (30) and transparent inorganic insulating layer (60)) is thicker than a second part of the insulating layer (gate insulating layer (30)), the first part being between (i) the gate electrode (11A) and (ii) a source electrode (12) and a drain electrode (21) of the insulated gate transistor, and the second part being between (i) the gate electrode (11A) and (ii) a channel section (31A) of the insulated gate transistor. This makes it possible to reduce parasitic capacitor without deteriorating characteristics of the transistor.

Abstract: Provided is an active matrix substrate manufacturing method, including the steps of: selectively forming a laminated structure pattern, by forming the laminated structure on a glass substrate (2), by forming a first photosensitive resin pattern (PR) on the laminated structure, and by selectively forming the laminated structure pattern using the first photosensitive resin pattern (PR), the laminated structure including a metal layer (a scanning signal line (11) material), a gate insulative layer (30), and a semiconductor layer (31, 33) (transistor material); fluorinating a surface of the first photosensitive resin pattern (PR) by dry-etching with fluorine gas; applying a coating-type transparent insulative resin (60) onto the glass substrate (2) to fill a space in the laminated structure pattern; and removing the fluorinated first photosensitive resin pattern (PR).

Abstract: Provided is an active matrix substrate manufacturing method, including the steps of: selectively forming a laminated structure pattern, by forming the laminated structure on a glass substrate (2), by forming a first photosensitive resin pattern (PR) on the laminated structure, and by selectively forming the laminated structure pattern using the first photosensitive resin pattern (PR), the laminated structure including a metal layer (a scanning signal line (11) material), a gate insulative layer (30), and a semiconductor layer (31, 33) (transistor material); fluorinating a surface of the first photosensitive resin pattern (PR) by dry-etching with fluorine gas; applying a coating-type transparent insulative resin (60) onto the glass substrate (2) to fill a space in the laminated structure pattern; and removing the fluorinated first photosensitive resin pattern (PR).

Abstract: Provided is an active matrix substrate manufacturing method, including the steps of: selectively forming a laminated structure pattern, by forming the laminated structure on a glass substrate (2), by forming a first photosensitive resin pattern (PR) on the laminated structure, and by selectively forming the laminated structure pattern using the first photosensitive resin pattern (PR), the laminated structure including a metal layer (a scanning signal line (11) material), a gate insulative layer (30), and a semiconductor layer (31, 33) (transistor material); fluorinating a surface of the first photosensitive resin pattern (PR) by dry-etching with fluorine gas; applying a coating-type transparent insulative resin (60) onto the glass substrate (2) to fill a space in the laminated structure pattern; and removing the fluorinated first photosensitive resin pattern (PR).

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: Provided is an active matrix substrate manufacturing method, including the steps of: selectively forming a laminated structure pattern, by forming the laminated structure on a glass substrate (2), by forming a first photosensitive resin pattern (PR) on the laminated structure, and by selectively forming the laminated structure pattern using the first photosensitive resin pattern (PR), the laminated structure including a metal layer (a scanning signal line (11) material), a gate insulative layer (30), and a semiconductor layer (31, 33) (transistor material); fluorinating a surface of the first photosensitive resin pattern (PR) by dry-etching with fluorine gas; applying a coating-type transparent insulative resin (60) onto the glass substrate (2) to fill a space in the laminated structure pattern; and removing the fluorinated first photosensitive resin pattern (PR).

Abstract: According to the insulated gate transistor, a gate electrode (11A) is provided on a main surface of a glass substrate (2); a first part of an insulating layer (gate insulating layer (30) and transparent inorganic insulating layer (60)) is thicker than a second part of the insulating layer (gate insulating layer (30)), the first part being between (i) the gate electrode (11A) and (ii) a source electrode (12) and a drain electrode (21) of the insulated gate transistor, and the second part being between (i) the gate electrode (11A) and (ii) a channel section (31A) of the insulated gate transistor. This makes it possible to reduce parasitic capacitor without deteriorating characteristics of the transistor.

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens.

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: In the conventional manufacture method that has reduced the number of manufacture processes by forming semiconductor layers and source-drain wires for a channel-etch type insulating gate transistor in a single photo etching process using halftone exposure technology, the channel length increases when the photosensitive resin pattern used at above formation process of source-drain patterning is reduced. Hence the manufacture tolerance (margin) is small, and the yield decreases when the distance between the source wire and drain wire is shortened.

Abstract: A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drai

Abstract: In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens.

Abstract: Development of 3-mask process to reduce the manufacturing cost of LCD-display device successively following 4-mask process. Opening formation process and pixel electrode formation process which is sequentially done following the opening formation process are treated with one photo-mask without using halftone exposure technology by forming source-drain wires comprising a low-resistance metal layer and a heat-resistant metal layer, the latter is capable of being removed with etching gas for etching gate insulating layer (and passivation insulating layer), giving protection means at least for the channel and the data line of the insulating gate transistor, forming openings in the insulating layers including the gate insulating layer with photosensitive resins having counter-taper cross sections, removing the exposed low-resistance metal in the openings, forming pixel electrode with the photosensitive resins as a lift-off material to lift off the conductive thin film for pixel electrode.

Abstract: A method for providing a high-response and wide-viewing-angle liquid crystal panel capable of causing a transition of liquid crystal, called the OCB mode, into a bend configuration in a short time, by providing a period in which a potential difference higher than that in a normal image display period is continuously applied between gate lines and opposing electrodes or between pixel electrodes and the opposing electrodes of a liquid crystal panel.

Abstract: In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens.

Abstract: In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens.

Abstract: Four-mask and three-mask process for TN-type liquid crystal display made with combination of the formation process of the signal line and the formation process of the pixel electrode by forming a signal line of a laminate of a transparent conductive layer and a low-resistance metal layer and a pseudo-pixel electrode, removing a low resistance metal layer on the pseudo-pixel electrode during formation of an opening in a passivation insulating layer to obtain a pixel electrode having a transparent conductive layer. Contact formation process by removing the gate insulating layer during formation of the semiconductor layer, and the formation process of the contact and the formation process of the semiconductor layer, or the formation process of the scan line and the formation process of the contact or the formation process of the scan line and the formation process of the semiconductor layer by introducing half-tone exposure technology.

Abstract: In the conventional manufacture method that has reduced the number of manufacture processes by forming semiconductor layers and source-drain wires for a channel-etch type insulating gate transistor in a single photo etching process using halftone exposure technology, the channel length increases when the photosensitive resin pattern used at above formation process of source-drain patterning is reduced. Hence the manufacture tolerance (margin) is small, and the yield decreases when the distance between the source wire and drain wire is shortened.