Patents by Inventor Kiyomi Hagihara
Kiyomi Hagihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10847702Abstract: A semiconductor module includes: a semiconductor element; a wiring substrate on which the semiconductor element is mounted; a heat dissipation substrate; a first metal material that bonds the wiring substrate and the heat dissipation substrate; and a second metal material that bonds the wiring substrate and the heat dissipation substrate and has a different melting point from the first metal material. Each of the following is at least partially bonded: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, the second metal material and the wiring substrate, the second metal material and the heat dissipation substrate, and the first metal material and the second metal material. Each of the following is bonded by alloying: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, and the first metal material and the second metal material.Type: GrantFiled: February 26, 2019Date of Patent: November 24, 2020Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Takeshi Kawabata, Kiyomi Hagihara, Takashi Yui, Naofumi Koga
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Patent number: 10546988Abstract: A light emitting device includes a light emitting element; a sub-mount including a sub-mount substrate with a front surface on which the light emitting element is disposed, and a back surface electrode disposed in a back surface that is on a back side of the front surface of the sub-mount substrate; a main-mount in which the sub-mount is disposed, the main-mount including a front surface metal pattern including a wiring electrode bonded to the back surface electrode via solder. The front surface metal pattern has a slit, in a plan view, at a position away from a disposition region in which the sub-mount is disposed.Type: GrantFiled: February 1, 2018Date of Patent: January 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Masahiro Hayashi, Tetsuya Kamada, Takashi Kuwaharada, Kiyomi Hagihara, Toshikazu Shimokatano, Shigeo Hayashi, Hiroki Shirozono, Hideaki Usukubo
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Publication number: 20190189881Abstract: A semiconductor module includes: a semiconductor element; a wiring substrate on which the semiconductor element is mounted; a heat dissipation substrate; a first metal material that bonds the wiring substrate and the heat dissipation substrate; and a second metal material that bonds the wiring substrate and the heat dissipation substrate and has a different melting point from the first metal material. Each of the following is at least partially bonded: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, the second metal material and the wiring substrate, the second metal material and the heat dissipation substrate, and the first metal material and the second metal material. Each of the following is bonded by alloying: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, and the first metal material and the second metal material.Type: ApplicationFiled: February 26, 2019Publication date: June 20, 2019Inventors: Takeshi KAWABATA, Kiyomi HAGIHARA, Takashi YUI, Naofumi KOGA
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Patent number: 10305008Abstract: A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.Type: GrantFiled: October 18, 2017Date of Patent: May 28, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takeshi Kawabata, Kiyomi Hagihara, Satoshi Kanai, Takashi Yui
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Publication number: 20180159006Abstract: A light emitting device includes a light emitting element; a sub-mount including a sub-mount substrate with a front surface on which the light emitting element is disposed, and a back surface electrode disposed in a back surface that is on a back side of the front surface of the sub-mount substrate; a main-mount in which the sub-mount is disposed, the main-mount including a front surface metal pattern including a wiring electrode bonded to the back surface electrode via solder. The front surface metal pattern has a slit, in a plan view, at a position away from a disposition region in which the sub-mount is disposed.Type: ApplicationFiled: February 1, 2018Publication date: June 7, 2018Inventors: Masahiro HAYASHI, Tetsuya KAMADA, Takashi KUWAHARADA, Kiyomi HAGIHARA, Toshikazu SHIMOKATANO, Shigeo HAYASHI, Hiroki SHIROZONO, Hideaki USUKUBO
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Publication number: 20180040792Abstract: A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.Type: ApplicationFiled: October 18, 2017Publication date: February 8, 2018Inventors: Takeshi KAWABATA, Kiyomi HAGIHARA, Satoshi KANAI, Takashi YUI
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Patent number: 9589877Abstract: A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.Type: GrantFiled: January 8, 2014Date of Patent: March 7, 2017Assignee: Panasonic CorporationInventors: Shigefumi Dohi, Kiyomi Hagihara
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Patent number: 9474179Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: GrantFiled: August 7, 2015Date of Patent: October 18, 2016Assignee: PANASONIC CORPORATIONInventors: Yukitoshi Ota, Fumito Itou, Kiyomi Hagihara
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Patent number: 9443793Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.Type: GrantFiled: December 27, 2013Date of Patent: September 13, 2016Assignee: Panasonic CorporationInventors: Hiroki Yamashita, Takashi Yui, Takeshi Kawabata, Kiyomi Hagihara, Kenji Yokoyama
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Patent number: 9373595Abstract: In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal (4) of an electronic component (1) and an electrode terminal (5) of a substrate (2) contains an alloy (8) and a metal (9) having a lower modulus of elasticity than the alloy (8). The junction has a cross section structure in which the alloy (8) is surrounded by the metal (9) having the lower modulus of elasticity.Type: GrantFiled: August 8, 2012Date of Patent: June 21, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Daisuke Sakurai, Kazuya Usirokawa, Kiyomi Hagihara
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Publication number: 20150359119Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: ApplicationFiled: August 7, 2015Publication date: December 10, 2015Inventors: YUKITOSHI OTA, FUMITO ITOU, KIYOMI HAGIHARA
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Patent number: 9136219Abstract: A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.Type: GrantFiled: January 9, 2014Date of Patent: September 15, 2015Assignee: Panasonic CorporationInventors: Teppei Iwase, Kiyomi Hagihara
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Patent number: 9105463Abstract: A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.Type: GrantFiled: December 26, 2013Date of Patent: August 11, 2015Assignee: Panasonic CorporationInventors: Kenji Yokoyama, Takeshi Kawabata, Kiyomi Hagihara
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Patent number: 8866284Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.Type: GrantFiled: July 10, 2013Date of Patent: October 21, 2014Assignee: Panasonic CorporationInventors: Shouichi Kobayashi, Hiroaki Suzuki, Kazuhide Uriu, Koichi Seko, Takashi Yui, Kiyomi Hagihara
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Publication number: 20140217595Abstract: In a provided mounting structure, an electronic component such as a semiconductor chip having a fragile film is mounted on a substrate such as a circuit board with higher connection reliability. A junction that connects an electrode terminal (4) of an electronic component (1) and an electrode terminal (5) of a substrate (2) contains an alloy (8) and a metal (9) having a lower modulus of elasticity than the alloy (8). The junction has a cross section structure in which the alloy (8) is surrounded by the metal (9) having the lower modulus of elasticity.Type: ApplicationFiled: August 8, 2012Publication date: August 7, 2014Applicant: PANASONIC CORPORATIONInventors: Daisuke Sakurai, Kazuya Usirokawa, Kiyomi Hagihara
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Publication number: 20140124957Abstract: A semiconductor device includes: a first semiconductor chip having a surface provided with first electrodes; and an expanded semiconductor chip including a second semiconductor chip and an expanded portion extending outward from at least one side surface of the second semiconductor chip. The expanded semiconductor chip has a surface provided with second electrodes. The surface of the first semiconductor chip provided with the first electrodes faces the surface of the expanded semiconductor chip provided with the second electrodes so that the first electrodes are connected to the second electrodes. Each one of the second electrodes that is connected to an associated one of the first electrodes is located only on the expanded portion.Type: ApplicationFiled: January 9, 2014Publication date: May 8, 2014Applicant: PANASONIC CORPORATIONInventors: TEPPEI IWASE, KIYOMI HAGIHARA
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Publication number: 20140117542Abstract: A semiconductor device includes an expanded semiconductor chip having a first semiconductor chip and an expanded portion extending outward from a side surface of the first semiconductor chip, a second semiconductor chip provided so as to be connected to the expanded semiconductor chip via a plurality of first bumps, and a base provided so as to be connected to the expanded semiconductor chip via a plurality of second bumps. The first bumps are provided between the first semiconductor chip and the second semiconductor chip. The second bumps are provided between the expanded portion and the base.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: Panasonic CorporationInventors: SHIGEFUMI DOHI, KIYOMI HAGIHARA
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Publication number: 20140103544Abstract: A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: KENJI YOKOYAMA, TAKESHI KAWABATA, KIYOMI HAGIHARA
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Publication number: 20140103504Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.Type: ApplicationFiled: December 27, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: HIROKI YAMASHITA, TAKASHI YUI, TAKESHI KAWABATA, KIYOMI HAGIHARA, KENJI YOKOYAMA
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Publication number: 20130299957Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.Type: ApplicationFiled: July 10, 2013Publication date: November 14, 2013Inventors: SHOUICHI KOBAYASHI, HIROAKI SUZUKI, KAZUHIDE URIU, KOICHI SEKO, TAKASHI YUI, KIYOMI HAGIHARA