Patents by Inventor Kiyoshi Inoue
Kiyoshi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9895911Abstract: When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.Type: GrantFiled: November 18, 2016Date of Patent: February 20, 2018Assignee: Sharp Kabushiki KaishaInventor: Kiyoshi Inoue
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Publication number: 20170066263Abstract: When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.Type: ApplicationFiled: November 18, 2016Publication date: March 9, 2017Inventor: Kiyoshi INOUE
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Patent number: 9535383Abstract: When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.Type: GrantFiled: April 15, 2011Date of Patent: January 3, 2017Assignee: SHARP KABUSHIKI KAISHAInventor: Kiyoshi Inoue
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Patent number: 9007830Abstract: A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.Type: GrantFiled: August 6, 2013Date of Patent: April 14, 2015Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Publication number: 20140185380Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: August 6, 2013Publication date: July 3, 2014Applicant: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
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Patent number: 8503235Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 17, 2011Date of Patent: August 6, 2013Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 8331153Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.Type: GrantFiled: February 1, 2012Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20120213002Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 17, 2011Publication date: August 23, 2012Inventors: Kunihiro KATAYAMA, Takayuki TAMURA, Satoshi WATATANI, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
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Publication number: 20120127792Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 8156779Abstract: In an apparatus for producing a spark plug, approach driving conditions are calculated on the basis of a specified thrust feeding amount so that, while a temporal overlap occurs between a time period of feed-driving toward a rolling position P2 of a workpiece supporting portion (11) and an approach driving time period, in a circumferential direction of a workpiece W, a positional relationship between the starting position of the threaded portion which is rolling-formed, and the joining position of the ground electrode to the tip end face of the workpiece W is constant. The operation of an approach driving portion is controlled on the basis of the calculated approach driving conditions.Type: GrantFiled: November 22, 2007Date of Patent: April 17, 2012Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Ohashi, Kiyoshi Inoue, Masato Nagasaki, Yasuhiro Hori
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Patent number: 8134869Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: August 10, 2011Date of Patent: March 13, 2012Assignee: Renesas Electronics CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20110292727Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: August 10, 2011Publication date: December 1, 2011Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 8064257Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 10, 2009Date of Patent: November 22, 2011Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Publication number: 20110255131Abstract: When trial printing is executed in a repeat printing mode, trial printing is performed in size of an image of one piece in a layout in which a plurality of images are supposed to be printed in the repeat printing mode normally. A user who has checked a finished state of the trial printing sets, when the finished state is in a desired state, the recording paper on which the trial printing is performed to the paper feed portion again and executes the repeat printing. Thereby, in a blank space excluding a print image which is printed with a first time trial printing, a scheduled quantity of a plurality of images are repeatedly printed.Type: ApplicationFiled: April 15, 2011Publication date: October 20, 2011Applicant: SHARP KABUSHIKI KAISHAInventor: Kiyoshi Inoue
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Patent number: 8023325Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: February 1, 2011Date of Patent: September 20, 2011Assignee: Renesas Technology CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20110122701Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: ApplicationFiled: February 1, 2011Publication date: May 26, 2011Inventors: Kunihiro KATAYAMA, Takayuki Tamura, Kiyoshi Inoue
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Patent number: 7895857Abstract: An indoor unit of an air conditioner wherein a pipe retaining member retaining auxiliary piping connected to a heat exchanger is disposed near both a lateral side and an underside of a mounting frame. The pipe retaining member is bent in an L-shape, and its short plate is exposed on the underside of the mounting frame. The pipe retaining member can be removed only by slightly separating a lower part of the mounting frame from a wall in the fixed state of the indoor unit to the wall. Since the heat exchanger can be separated from the mounting frame without disconnecting the auxiliary piping from communication piping, maintenance work such as washing of the heat exchanger is efficiently performed without requiring much time and effort for separating the auxiliary piping from the communication piping.Type: GrantFiled: September 9, 2005Date of Patent: March 1, 2011Assignee: Daikin Industies, Ltd.Inventors: Kiyoshi Inoue, Katsuhiro Wakihara, Toshiaki Yamada, Ikuhiro Yamada, Shiro Kashiwa
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Patent number: 7881111Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.Type: GrantFiled: July 16, 2009Date of Patent: February 1, 2011Assignee: Renesas Technology CorporationInventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
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Publication number: 20100177579Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 10, 2009Publication date: July 15, 2010Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 7724249Abstract: Terminal equipment for electronically making patent and utility patent applications. The terminal equipment converts various formats of text data generated by an external device into the internal format of the terminal equipment, retrieves the converted text data, merges the text data with a procedure, and transmits the procedure. The merging operation in which image data is merged with text data is simplified whereby the operator can make applications with a simple operation without special skill and knowledge when an application document is transmitted and received on line.Type: GrantFiled: April 30, 1991Date of Patent: May 25, 2010Assignee: Fujitsu LimitedInventors: Akira Horikawa, Masanori Kawaguchi, Hirotoshi Umemura, Tetsuo Aoki, Atsurou Noguchi, Kouichi Masaki, Akihiko Shigeta, Kiyoshi Ohi, Kiyoshi Inoue, Yasuhiro Tameie, Naruhito Yamamoto, Hiroshi Aihara, Masahiko Senda