Patents by Inventor Kiyoshi Inoue

Kiyoshi Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040022249
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Application
    Filed: July 30, 2003
    Publication date: February 5, 2004
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Publication number: 20040019863
    Abstract: A circuit verification apparatus, a circuit verification program and a circuit verification method are provided in which in the verification of a circuit according to software, the probability that an accumulation circuit such as a queue circuit, etc., changes into a saturated state can be increased without changing the logic of the circuit to be verified, thus making it possible to shorten the time required for the circuit verification.
    Type: Application
    Filed: January 6, 2003
    Publication date: January 29, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Kiyoshi Inoue
  • Patent number: 6683812
    Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
  • Patent number: 6642189
    Abstract: Engine oil compositions are provided containing (A) a lubricating base oil having a kinematic viscosity at 100° C. of 3 to 6 mm2/S, a viscosity index of 120 or more, and a total aromatic content of 5 percent by mass or less and (B) a polymethacrylate-based viscosity index improver, preferably having a weight average molecular weight of 180,000 or more, (A) and (B) being blended in such an amount that the composition has a kinematic viscosity at 100° C. of 4.0 to 9.3 mm2/s. The engine oil compositions may also contain a molybdenumdithiocarbamate, as well as one or more other engine oil additives. The engine oil compositions preferably have a high-temperature, high shear viscosity at 150° C. of 2.4 to 2.7 mPa·s, a NOACK evaporation loss of 16 percent by mass or less, and a CCS viscosity at −25° C. of 3500 mPa·s or less.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: November 4, 2003
    Assignee: Nippon Mitsubishi Oil Corporation
    Inventors: Isao Kurihara, Jinichi Igarashi, Kiyoshi Inoue
  • Publication number: 20030202296
    Abstract: A power supply device 3 including: a current source 31 for supplying current to a load circuit 4 which operates on the supplied current, and a power switch unit 32 between the current source 31 and the load circuit 4 to control passage of current, wherein: the power switch unit 32 includes a switching element 323 connected in parallel with the open-close element 321, a power supply controller 33 including an open-close element controller 31 which controls operation of the open-close element 321 and a switching element controller 332 which controls operation of the switching element 323, and a voltage detector 34 which detects terminal voltage of the load circuit 4; and the power switch unit 32 turns on the switching element before supplying current to the load circuit and closes the open-close element when the terminal voltage of the load circuit becomes almost equal to supply voltage.
    Type: Application
    Filed: April 24, 2003
    Publication date: October 30, 2003
    Inventors: Yoshiomi Hamano, Kiyoshi Inoue, Junichi Kajiwara, Takao Horiuchi, Koichi Sumida, Akira Tamagaki, Akihiko Taniguchi, Hiroki Kai
  • Patent number: 6628889
    Abstract: Data including video data and audio data recorded on a tape-like recording medium of a video cassette 12 are read, and position information of at least the video data of the data including the video data and the audio data stored in a cassette-appendant memory as temporary storage means of the video cassette 12 is read. The data including the video data and the audio data read from the tape-like recording medium are edited. The position information is relocated, or the position information is relocated while position information is newly prepared, thereby preparing editing data. Thus, a target portion in the case of up-loading the video data and the audio data from the video cassette 12 to an editing device 14 or the like may be designated in a short period of time.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: September 30, 2003
    Assignee: Sony Corporation
    Inventor: Kiyoshi Inoue
  • Patent number: 6627583
    Abstract: An engine oil composition characterized by containing a major amount of lubricating base oil and (a) 0.01 to 30% by weight of an overbasic oil-soluble metal salt prepared by use of an alkaline-earth metal borate, (b) 0.01 to 5% by weight of a molybdenum dithiocarbamate, and (c) 0.01 to 5% by weight of an antioxidant as essential components, on the basis of the total amount of the composition.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: September 30, 2003
    Assignee: Nippon Mitsubishi Oil Corporation
    Inventors: Kiyoshi Inoue, Jinichi Igarashi, Mituaki Ishimaru, Mineo Kagaya, Masakuni Hirata
  • Publication number: 20030162673
    Abstract: Engine oil compositions are provided containing (A) a lubricating base oil having a kinematic viscosity at 100° C. of 3 to 6 mm2/S, a viscosity index of 120 or more, and a total aromatic content of 5 percent by mass or less and (B) a polymethacrylate-based viscosity index improver, preferably having a weight average molecular weight of 180,000 or more, (A) and (B) being blended in such an amount that the composition has a kinematic viscosity at 100° C. of 4.0 to 9.3 mm2/s. The engine oil compositions may also contain a molybdenumdithiocarbamate, as well as one or more other engine oil additives. The engine oil compositions preferably have a high temperature, high shear viscosity at 150° C. of 2.4 to 2.7 mPa·s, a NOACK evaporation loss of 16 percent by mass or less, and a CCS viscosity at −25° C. of 3500 mPa·s or less.
    Type: Application
    Filed: December 12, 2002
    Publication date: August 28, 2003
    Applicant: Nippon Mitsubishi Oil Corporation
    Inventors: Isao Kurihara, Jinichi Igarashi, Kiyoshi Inoue
  • Publication number: 20030132699
    Abstract: Phosphors for a display, which emit blue light and green light, comprise zinc sulfide phosphors having a crystal structure of a hexagonal system. The zinc sulfide phosphor which emits blue light has an average particle diameter in a range of (0.0169×VE1.9+2.49)±20%[&mgr;m] when an electron beam has an acceleration voltage VE. The zinc sulfide phosphor which emits green light has an average particle diameter in a range of (0.017×VE1.9+2.58)±20%[&mgr;m]. A phosphor for a display, which emits red light, comprises a yttrium oxysulfide phosphor or a yttrium oxide phosphor and has an average particle diameter in a range of (0.023×VE1.95+2.88)±20%[&mgr;m]. These phosphors for a display are used for a display which has an electron beam having an acceleration voltage of 3 kV to 15 kV as an excitation source.
    Type: Application
    Filed: October 10, 2002
    Publication date: July 17, 2003
    Inventors: Kenichi Yamaguchi, Kiyoshi Inoue, Susumu Matsuura, Takeo Ito
  • Publication number: 20030128585
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Application
    Filed: February 27, 2003
    Publication date: July 10, 2003
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Patent number: 6580224
    Abstract: A backlight for color liquid crystal comprises a light-emitting layer having EL phosphor particles dispersed in a matrix of dielectrics, a transparent electrode layer disposed along a main surface on an emitting side of a light-emitting layer, and a reflective insulating layer and a rear electrode layer stacked in turn along a main surface on a non-emitting side of a light-emitting layer. An EL element, under the operational conditions of a voltage of 100 Vrms and a frequency of 400 Hz, emits white light of which brightness is 80 cd/m2 or more, and has characteristics of consumption power of 30 W/m2 or less. By the use of such EL element as a backlight, a color liquid crystal display device that is low in consumption power, excellent in display performance and suitable for a display portion of a portable information terminal can be provided.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: June 17, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Ishii, Mitsuo Nakamura, Kiyoshi Inoue
  • Publication number: 20030072203
    Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 17, 2003
    Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
  • Patent number: 6542405
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 1, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Patent number: 6508889
    Abstract: A high-performance Nb3Al extra-fine multifilamentary superconducting wire is produced simply and inexpensively through the improvement of critical values, Tc, Hc2 and Jc, without the addition of third elements such as Ge, Si and Cu. A first rapid heating and quenching treatment is applied to an Nb/Al composite wire having an atomic ratio of Al to Nb from 1:2.5 to 1:3.5 and having an extra-fine multifilamentary structure to form a BCC alloy phase comprising Nb with Al supersaturatedly dissolved therein wherein the treatment comprises heating the composite wire up to a temperature not lower than 1900° C. within two seconds and then introducing it into a molten metal at a temperature not higher than 400° C. to rapidly quench it.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: January 21, 2003
    Assignee: National Institute for Materials Science
    Inventors: Akihiro Kikuchi, Yasuo Iijima, Kiyoshi Inoue
  • Patent number: 6493273
    Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
  • Publication number: 20020106187
    Abstract: Data including video data and audio data recorded on a tape-like recording medium of a video cassette 12 are read, and position information of at least the video data of the data including the video data and the audio data stored in a cassette-appendant memory as temporary storage means of the video cassette 12 is read. The data including the video data and the audio data read from the tape-like recording medium are edited. The position information is relocated, or the position information is relocated while position information is newly prepared, thereby preparing editing data. Thus, a target portion in the case of up-loading the video data and the audio data from the video cassette 12 to an editing device 14 or the like may be designated in a short period of time.
    Type: Application
    Filed: November 23, 1998
    Publication date: August 8, 2002
    Inventor: KIYOSHI INOUE
  • Publication number: 20020097604
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Application
    Filed: March 26, 2002
    Publication date: July 25, 2002
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Patent number: 6388920
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Patent number: 6376099
    Abstract: A Cu-containing Nb3Al multifilamentary superconductive wire having a multifilamentary (superfine multi-core structure that a large number of micro-complex cores each obtained by complexing a Cu—Al alloy containing Cu in an amount of more than 0.2 at. % and at most 10 at. % in Nb are embedded in Nb, Ta, an Nb alloy or a Ta alloy as a matrix, wherein in the micro-complex cores, an A15 phase compound structure is formed by rapid heating at a temperature of 1,700° C. or more for 2 seconds or less and quenching to approximately room temperature, and further additionally heat-treated at a temperature of 650 to 900° C. This superconductive wire has high Jc in a low magnetic field, can be applied to all magnetic fields of 29 T or less, and is excellent in Jc characteristics in a high magnetic field in comparison with an Nb3Al wire.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: April 23, 2002
    Assignee: Agency of Industrial Science and Technology National Research Institute for Metals
    Inventors: Kiyoshi Inoue, Yasuo Iijima, Akihiro Kikuchi
  • Patent number: 6372054
    Abstract: A process for producing an ultrafine multifilamentary superconducting Nb3(Al,Ge) wire capable of generating a high critical current density comprising: preparing a composite core material comprising an A1—(2-30)at. % Ge alloy (where at. % represents % by atomic) 1 &mgr;m or less in thickness uniformly incorporated into a Nb matrix at a volume ratio in a range of 1:2.5 to 1:3.5 and forming a composite therewith; fabricating a composite wire having an ultrafine multifilamentary structure by embedding several tens to several millions of the resulting composite core materials in a cylindrical matrix material containing Nb; forming a A15-phase filament having a lower order in crystallinity inside the composite wire by a rapid heating and quenching treatment comprising rapidly heating to a temperature of 1,700° C.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: April 16, 2002
    Assignee: Japan as represented by Director General of National Research Institute for Metals
    Inventors: Akihiro Kikuchi, Yasuo Iijima, Kiyoshi Inoue