Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

Abstract: A semiconductor memory device includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells, each formed of a MIS transistor, are disposed at intersections of the word lines and the bit lines. The threshold voltages of the MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof. The floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells. A first row decoder applies a normal voltage to a selected word line to select memory cells connected to the selected word line, when reading data. A second row decoder applies a predetermined source voltage to sources of memory cells connected to the selected word line, and applies an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory comprises a p-type silicon substrate including a first diffused layer and a second diffused layer, and a gate insulation film in which carriers are trapped in different areas. A first voltage and a second voltage are applied to the p-type silicon substrate and the gate electrode, respectively, to allow tunnel current to flow between the p-type silicon substrate and the gate electrode so that the tunnel current may eliminate the carriers trapped in the gate insulation film. This allows all the electrons captured in the central portion of the channel area to disappear, resulting in more reliable data erasure.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory comprises a p-type silicon substrate including a first diffused layer and a second diffused layer, and a gate insulation film in which carries are trapped in different areas. A first voltage and a second voltage are applied to the p-type silicon substrate and the gate electrode, respectively, to allow tunnel current to flow between the p-type silicon substrate and the gate electrode so that the tunnel current may eliminate the carries trapped in the gate insulation film. This allows all the electrons captured in the central portion of the channel area to disappear, resulting in more reliable data erasure.

Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.

Abstract: The present invention relates to a semiconductor device including an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on an S/D region adjacent to a gate electrode and has an object to provide a semiconductor device capable of securing the uniformity of the thickness of an insulating film between a gate electrode and an S/D electrode or interconnection layer while integrating elements at a high density. The semiconductor device comprises an S/D region formed in a semiconductor layer at the both sides of the gate electrode, an insulating side wall formed on side surface of the gate electrode, a conducting side wall covering side surface of the insulating side wall and contacting the S/D region, a covering insulating film for covering the gate electrode, S/D region, insulating side wall, and conducting side wall, and a contact hole formed in the covering insulating film on the S/D region of at least one side.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: The present invention relates to a semiconductor device including an insulated-gate field effect transistor having a contact hole formed in an inter-layer insulating film on an S/D region adjacent to a gate electrode and has an object to provide a semiconductor device capable of securing the uniformity of the thickness of an insulating film between a gate electrode and an S/D electrode or interconnection layer while integrating elements at a high density. The semiconductor device comprises an S/D region formed in a semiconductor layer at the both sides of the gate electrode, an insulating side wall formed on side surface of the gate electrode, a conducting side wall covering side surface of the insulating side wall and contacting the S/D region, a covering insulating film for covering the gate electrode, S/D region, insulating side wall, and conducting side wall, and a contact hole formed in the covering insulating film on the S/D region of at least one side.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A nonvolatile semiconductor memory having a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the memory cells is provided at each intersection of the bit lines and the word lines. The nonvolatile semiconductor memory includes a plurality of latch units provided for each corresponding bit line, and a control circuit. The control circuit is used to supply a control voltage and a control signal to the latch units, to operate the latch units as units for simultaneously biasing voltages applied to first electrodes of specified memory cells through the bit lines during a write operation, to simultaneously write data into the specified memory cells, and during a read operation, as units for simultaneously reading data out of the memory cells. This memory has an inexpensive simple structure for carrying out a simple programming operation at high speed.

Abstract: A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.

Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.