Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.

Abstract: An exclusive OR circuit includes a first series circuit in which a source of a first pMIS transistor is connected to a positive-voltage power supply line. A drain of the first pMIS transistor is connected to a drain of a first nMIS transistor via a second nMIS transistor. The source of the first nMIS transistor is connected to a low-voltage power supply line via a fourth nMIS transistor. A second series circuit has a drain of a third nMIS transistor connected to a high-voltage power supply line via a second pMIS transistor. The source of the third nMIS transistor is connected to the source of a third pMIS transistor. The drain of the third pMIS transistor is connected to the low-voltage power supply line via a fourth pMIS transistor. The gates of the first and third nMIS transistors and the first and third pMIS transistors are connected to one another and provided with a first input.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.

Abstract: A non-volatile semiconductor device includes a bus line; a plurality of bit lines coupled to the bus line; a cell transistor, connected between each of the bit lines and a word line, for storing electrical information; an output circuit, coupled to the bus line, for outputting a signal corresponding to the electrical information stored in the cell transistor under a condition in which the bus line has been charged to a predetermined voltage level; a constant voltage circuit coupled to the bus line, the constant voltage circuit generating a voltage having an approximately constant level when a current flows through the constant voltage circuit; and a current supply circuit, coupled to the bus line, for supplying a current to the constant voltage circuit via the bus line in accordance with a control signal supplied from an external unit, whereby the bus line is charged to a predetermined voltage level by the voltage generated by the constant voltage circuit.

Abstract: A programmable logic device includes an input/output buffer, a logic array, switches for switching signal lines provided between the logic array and the input/output buffer and feedback lines between an input and an output of the logic array so as to alter the logic operation. Switching operations of the switches such as an open/close operation and a selection operation, are determined by the data stored in a plurality of non-volatile memory elements arranged in a matrix of rows and columns, the non-volatile memory elements being respectively associated with the switches. The contents of the memory elements are read out and stored in registers. The data contents of the non-volatile memory elements as thus stored in the registers are applied to control terminals of the switches.

Abstract: A programmable logic device includes an AND array; an OR array; a buffer circuit connected between the AND array and OR array; and a number of decoder arrangements operatively connected to the AND array and OR array. By constituting the buffer such that the AND array and OR array are electrically associated even in a write operation of data, namely, the buffer is brought to an enable state, a logic verify of the buffer becomes unnecessary and, accordingly, a verify/check of written data can be carried out both easily and efficiently.

Abstract: A semiconductor integrated circuit device has a plurality of terminals, an internal circuit for receiving input signals from the terminals and for outputting output signals to the terminals, where the internal circuit is enabled by a chip enable signal and disabled by a chip disable signal, a non-volatile memory for storing a pin select signal which designates at least a selected one of the terminals as a chip enable control terminal for receiving a control signal which has a first logic level when instructing a power down mode of the semiconductor integrated circuit device, and a buffer part coupled to the terminals and the non-volatile memory for generating the chip enable signal and the chip disable signal responsive to the pin select signal and the control signal.

Abstract: A programmable logic array circuit includes a pulse signal generating circuit for generating a pulse signal by detecting a change in levels of input signals. A first transistor for precharging a product term line is provided. A second transistor is provided for discharging an OR array input line. A third transistor is provided for precharging an OR array output line. The first through third transistors are controlled by the pulse signal. In other words, the first through third transistors are controlled in response to the signal change of the input signals. In order to facilitate the discharging operation with respect to the OR array input line, a fourth transistor may be provided on a side opposite to the second transistor.

Abstract: An integrated semiconductor circuit device for generating a switching control signal includes a fuse having one terminal connected to a power source, and the other terminal connected to a flip-flop circuit comprising a cross-connected pair of complementary MOS field effect transistor type inverters. The output of the flip-flop circuit can be used as the switching control signal for a semiconductor memory device having a redundant circuit.

Abstract: A semiconductor memory device includes a plurality of word lines and a plurality of bit lines arranged perpendicular to each other. Memory cells are located at the cross position between each word line and each bit line, and one of the bit lines is selected by the operation of a bit line selection transistor driven by the signal of a column decoder. The bit line selection transistors are separated into a plurality of blocks corresponding to each bit line group, and the bit line selection transistors in each block are arranged along the direction of the bit line. Further, the gates of the bit line selection transistors are arranged perpendicular to the direction of the bit lines, and the gates of the bit line selection transistors are commonly connected to the gates of the corresponding bit line selection transistors in the adjoining bit line selection transistor blocks.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks corresponding to output terminals, and a redundancy memory cell block for replacing a faulty memory cell block among the memory cell blocks, the redundancy memory cell block having a first specific area for storing a first predetermined data of electronic signatures. Each of the memory cell blocks having a second specific area for storing a second predetermined data equal to a divided one of the first predetermined data in a one to one correspondence. The semiconductor memory device further includes a circuit for selectively reading, when one of the memory cell blocks is replaced by the redundancy memory cell block, a divided one of the first predetermined data corresponding to the second predetermined data stored inthe memory cell block to be replaced by the redundancy memory cell block. The second predetermined data can be correctly read out even when a faulty memory cell block is replaced with the redundancy memory cell block.