Abstract: An overcurrent is detected with small power consumption and at a high level of accuracy. A first transistor section 3 comprised of one NPN transistor 31 and a second transistor section 4 comprised of four NPN transistors 41-44 having the same characteristics as those of the transistor 31 are connected across a current sense resistor 2, with their emitters connected to the resistor 2. The transistors 31 and 41-44 have their bases commonly connected, with a voltage applied between their base and emitter by a voltage application unit 5, and have their collectors connected to transistors 61 and 62 which form a current mirror circuit. Once a bandgap voltage, .DELTA.V.sub.BE, i.e., a voltage difference between the base-emitter voltages of the transistor sections 3 and 4, is determined, the current density ratio of both the transistor sections 3 and 4 is determined, which is used to detect an overcurrent.

Abstract: A delay line having feedback from a control circuit at the output of the delay line controls the delay line duty cycle to within a specified range. The delay line comprises at least one delay unit having control inputs to each delay unit. The output of the delay line feeds to a low-pass filter (LPF). A voltage proportional to the duty cycle of the delay line output is generated within the LPF and fed to a differential amplifier. The differential amplifier is in turn coupled to the control inputs of each of the delay units. When the voltage signal from the LPF is high (duty cycle is high), the differential amplifier will generate a signal causing the fall time of the signal propagating through the delay line to increase and rise time to decrease. This will decrease the high cycle time at the output of the delay line. When the voltage signal from the LPF is low (duty cycle is low), the differential amplifier will generate a signal causing the fall time to decrease and the rise time to increase.

Abstract: A differential amplifier avoids gain fluctuations due to process differences and changes in temperature and allows adjustability of the gain and associated frequency characteristics to desired gain values. The amplifier comprises a pair of load transistors coupled to a pair of differential input transistors. A pair of biased current source transistors assure a constant current through the differential transistors, and a pair of bias transistors supply a constant bias to the source of the load transistors. The gain is varied by varying the voltage supplied to the gates of the two load transistors. The voltage supplied to the load transistors is varied by varying the current supplied through a second pair of bias transistors. A number of current source transistors coupled in parallel vary the voltage through the second pair of bias transistors.

Abstract: Two storage capacitors connected in parallel with a constant current source in a charging mode and connected in series in a second mode to increase output voltage. A comparator senses the amplitude of the output voltage and controls the current supplied to the capacitors in the charging mode to increase or decrease the output voltage to coincide with a predetermined amplitude.

Abstract: This invention relates to a bias current control circuit which drives a power MOS transistor. Since the power MOS transistor has a large capacitance which is formed between a gate and a channel, it is needed to provide a circuit which is able to sufficiently supply a drive current to the gate. Such a circuit increases a consumption current because the circuit has to always flow the current to drive the gate. This invention provides a circuit which cut the consumption current in the circuit when the transistor is not driven, and increases a consumption current in the circuit in order to keep a gate current when the transistor is driven.

Abstract: Apparatus and procedure for testing a flash analog-to-digital converter on a chip including a first NOR gate having a plurality of inputs, one each connected to each normal output of the comparators and a second NOR gate having a plurality of inputs, one each connected to each inverted output of the comparators. The output currents of the NOR gates are monitored to determine the states of the comparators when various input voltages are supplied. All comparators are tested for operation.

Abstract: A microprocessor including a CPU, an instruction memory (ROM) with a sequencer in the CPU that sends out a fetch signal for an instruction, and an address decoder that decodes the fetch signal and sends a signal to the ROM allowing the fetch signal to fetch an instruction if the address is correct.

Abstract: A differential pair of transistors (Q2, Q3), the sources of which are connected to a current source (Q1); first and second input terminals (IN, VX) connected to the gates of the first and second transistors respectively; first and second output terminals (DN, DP) connected to the drains of the second and first transistors; third and fourth transistors (Q6, Q7), the sources of which are connected to a voltage supply (UDD), the drain of the third transistor being connected to the drain of the first transistor, and the drain of the fourth transistor being connected to the drain of the second transistor; the gate of the third transistor being connected to the drain of the first transistor via first switch (Q104) and connected to the drain of the second transistor via a first capacitor (C1); and the gate of the fourth transistor being connected to the drain of the second transistor via second switch (Q5) and connected to the drain of the first transistor via a second capacitor (C2).

Abstract: An overload circuit detects input signals that are too high or too low in amplitude and generates a holding signal of a predetermined duration. The holding signal is applied to a data selector which normally passes the input signal to a shift register/majority gate but switches to supply the output of the majority gate to the shift register when a holding signal is present. Thus, the output is maintained constant during the predetermined durations when a holding singnal is present.

Abstract: A circuit for generating a pulse when a voltage (VDD) is applied thereto comprising an input (10) for receiving the applied voltage, an output (36), a first capacitor (16) connected to be charged from the input through a first switch (12), a second capacitor (18) connected to be charged from the first capacitor through a second switch (14), control means (34) for alternately enabling the first and second switches and switch means (20, 22, 24, 26) connected to the second capacitor for applying the applied voltage to the output when the voltage on the second capacitor is less than a predetermined value and for applying ground voltage to the output when the voltage on the second capacitor is greater than the predetermined value.