Abstract: A semiconductor apparatus according to the present invention comprises a current source increasing a current volume in compliance with a rise of a temperature and an oscillation circuit driven by the current of the current source and outputting a clock for refresh control. The semiconductor apparatus, preferably, further comprises a memory device performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof. The semiconductor apparatus, preferably, further comprises a constant voltage source generating a constant voltage using the current source, an oscillation circuit using the current of the current source, and a memory using the constant voltage generated by the constant voltage source as a reference voltage for a power supply circuit and performing the refresh in synchronization with the output clock of the oscillation circuit or the divided clock thereof.

Abstract: A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced.

Abstract: The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.

Abstract: A semiconductor memory device is provided with a plurality of memory blocks including a plurality of word lines and a plurality of bit line pairs intersecting the individual word lines, a plurality of memory cells provided at each of intersections where the individual word lines intersect the bit line pairs, and a plurality of sense amplifiers respectively provided in correspondence with the bit line pairs. The semiconductor memory device further comprises common data bus line pairs each connected via switch transistors to the corresponding memory blocks, a read/write amplifier for performing a data read/write operation through the common data bus line pairs on the memory blocks, and an SRAM cell electrically connected via switch transistors to each common data bus line pair.

Abstract: A row control circuit of a semiconductor memory device includes an oscillator as a clock oscillator for generating an internal clock, a D flipflop as a refresh request signal RFRQ generation circuit for generating a refresh request signal RFRQ synchronously with the internal clock, and a delay circuit, a NAND gate, an AND gate, a D flipflop, a delay circuit, an AND gate and an OR gate as refresh circuits. By using a refresh request signal RFRQ and an active signal ACT, internal refresh is performed internally in a DRAM separately from an external refresh command.

Abstract: A voltage booster power supply circuit using a first voltage VDD3 and a second voltage VDDM to boost the first voltage VDD3, which is higher than the second voltage, to provide a boosted voltage VPP. Thus, a high efficiency of generation of a boosted voltage can be achieved compared with a configuration in which only the second voltage is used to boost the first voltage. A detector circuit detects the boosted voltage VPP to control a voltage booster circuit.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

Abstract: A semiconductor integrated circuit includes a functional circuit and a power source voltage generating circuit used for operating the functional circuit. In the power source voltage generating circuit, output stage transistors are driven by comparing a plurality of reference voltages produced by a plurality of resistors connected in series to one another with output voltages of a plurality of differential amplifiers connected in parallel to one another and varying gate voltages.

Abstract: A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.

Abstract: A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

Abstract: The present invention is a semiconductor memory device provided with bit line pairs to which a plurality of memory cells are attached, a plurality of precharge circuits for precharging the bit line pairs to a first voltage that is different from a mean value between a high level and a low level, a bit line precharge power line for supplying the first voltage for precharging to the precharge circuits, a capacitor, a charging circuit for charging the capacitor, and transfer gate circuits for controlling connection and disconnection of the capacitor and the bit line precharge power line. The transfer gate circuits are controlled so that the capacitor and the precharge power line are connected during precharging of the bit line pairs. Thus, precharging of the bit lines can be performed at high speeds with high precision.

Abstract: In a single intersection type (open bit line type) dynamic RAM, sub-arrays are disposed to the left and right sides of a sense amplifier column placed at the center. Each sub-array has a multiplicity of dynamic memory cells. In the subarrays located to the left and right of the sense amplifier column, bit lines in the same row constitute a complementary bit line pair. In each subarray, shielding wiring patterns that are formed parallel to, and in the same wiring layer of, these bit lines are disposed between the bit lines. All of these wiring patterns are set at a fixed potential, such as a power supply potential. Thus, interference noise between adjacent bit lines is effectively reduced.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: When a data read operation is requested, for example, a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated as sense amplifiers start amplifying data of corresponding memory cells. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. Moreover, the sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation. Thus, it is no longer necessary to perform an auto refresh operation.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: A semiconductor device capable of refreshing a plurality of memory cells. In operation, when requesting a data read operation a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. The sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation.

Abstract: Each of a plurality of sense amplifiers in a sense amplifier drive circuit of a DRAM includes a PMOS sense amplifier drive transistor and an NMOS sense amplifier drive transistor. The source of each of the PMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. The source of each of the NMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. Therefore, charging current and discharging current are distributed to the multiple power lines arranged in mesh-like pattern. Therefore, in sensing operations, the charging and the discharging currents in bit lines are distributed so that interference between the sense amplifiers can be suppressed and the data read-out speed can be increased.

Abstract: A semiconductor integrated circuit includes a functional circuit and a power source voltage generating circuit used for operating the functional circuit. In the power source voltage generating circuit, output stage transistors are driven by comparing a plurality of reference voltages produced by a plurality of resistors connected in series to one another with output voltages of a plurality of differential amplifiers connected in parallel to one another and varying gate voltages.

Abstract: When a data read operation is requested, for example, a /row selection control signal is input to a set/reset circuit of a row selection control circuit, whereby an H-level hidden refresh control signal is output and an internal row selection control signal transitions to the H level. As a result, an intended word line is selected, and a refresh operation is initiated as sense amplifiers start amplifying data of corresponding memory cells. Then, a sense amplifier activation completion signal SEND is input via a delay circuit to the set/reset circuit after completion of a sense operation, and the internal row selection control signal transitions to the L level. Moreover, the sense amplifier activation completion signal SEND is input to another set/reset circuit after passing through three delay circuits, and an RW row selection control signal transitions to the H level, thereby performing a data read operation. Thus, it is no longer necessary to perform an auto refresh operation.