Abstract: Each of a plurality of sense amplifiers in a sense amplifier drive circuit of a DRAM includes a PMOS sense amplifier drive transistor and an NMOS sense amplifier drive transistor. The source of each of the PMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. The source of each of the NMOS sense amplifier drive transistors is connected to a first common power line and to multiple independent power lines orthogonal thereto. Therefore, charging current and discharging current are distributed to the multiple power lines arranged in mesh-like pattern. Therefore, in sensing operations, the charging and the discharging currents in bit lines are distributed so that interference between the sense amplifiers can be suppressed and the data read-out speed can be increased.

Abstract: In a conventional DRAM, row addresses and column addresses are latched by DFF and decoding of addresses is started a certain time after a clock rise, and it takes a long time after the clock rise until the decoding is completed, having a problem that it is not possible to perform read/write at high speed. The present invention adopts a configuration connecting latch circuits such as the row address latch circuits and column address latch circuits using a scan chain. This makes decoding of row addresses and column addresses start when the clock is “L”, making it possible to complete decoding on the rise of each operation clock cycle, shorten the operation clock cycle and speed up read/write. The conventional art conducts a test on the connection between the row addresses and column addresses of the logic section and memory through an actual operation test of the entire LSI, resulting in a low circuit failure detection rate.

Abstract: A semiconductor integrated circuit is provided in which a negative voltage generation circuit capable of supplying a memory cell transistor substrate with a stable negative voltage, independently of the fluctuation of a power source voltage or environmental conditions and the process conditions etc., is realized easily, and in which the data holding time of a memory can be secured sufficiently, and the power consumption is reduced.

Abstract: The semiconductor memory device formed on a semiconductor substrate includes: a memory cell array having a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit line pairs; a plurality of sense amplifiers each formed to correspond to each of the plurality of bit line pairs for amplifying a potential difference read on the bit line pair; and a low-level potential generation section for generating a low-level potential out of high-level and low-level potentials to be applied to the memory cells, the bit line pairs, and the sense amplifiers.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of word lines selectively activated by a row address signal from the outside, a plurality of bit lines selected by a column address signal from the outside, and sense amplifiers connected to the bit lines. The device further includes a row address latch circuit for latching the row address signal by using, as a trigger, a first edge of a clock signal from the outside, a sense amplifier activating circuit for activating the sense amplifier after a lapse of a given time from the first edge, a column address latch circuit for latching a column address signal by using, as a trigger, a second edge of the clock signal occurring after the first edge, and a precharge signal generating circuit for generating a precharge signal for precharging the bit lines after a lapse of a given time from the second edge.

Abstract: In a memory device, a shift-register comprises a plurality of stages for transferring sequentially a pair of signals which have mutually opposite phases. Each stage has a comparator circuit which compares the pair of signals and generates a pair of fixed voltage signals. By this construction, high-speed operation of the memory device, low power consumptions, and high-capacity load driving are achieved.

Abstract: In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

Abstract: In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized.