Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.

Abstract: An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.

Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

Abstract: An integrated circuit arrangement is disclosed having a wiring indentation and an auxiliary indentation in a dielectric layer. The wiring indentation contains a metal through which current flows during operation of the circuit arrangement. The auxiliary indentation contains a metal through which an electric current does not flow during operation of the circuit arrangement. The auxiliary indentation serves as an alignment mark during the production of the integrated circuit arrangement.

Abstract: One or more embodiments relate to a semiconductor chip including a capacitor arrangement, the capacitor arrangement comprising: a first capacitor; and a second capacitor stacked above the first capacitor, the first capacitor and the second capacitor coupled in series between a first metallization level and a second metallization level adjacent the first metallization level.

Abstract: The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.

Abstract: A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses.

Abstract: A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode.

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects.

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

Abstract: A method of producing a capacitor that includes producing a first electrode having a first surface; forming a recess in an element, walls of the element and the first surface of the first electrode defining the recess, the element having a first surface exterior of the recess; forming a dielectric layer on the element, the dielectric layer oriented against the first surface of the element and against the walls of the element within the recess; polishing off at least a portion of the dielectric layer oriented against the first surface of the element to electrically isolate the portion of the dielectric layer located in the recess from any portion of the dielectric layer remaining outside the recess; and producing a second electrode, the second electrode oriented at least partially within the recess with the dielectric layer oriented between the first electrode and the second electrode.

Abstract: An integrated circuit arrangement containing a via is disclosed. The via has an upper section having greatly inclined sidewalls. A lower section of the via has approximately vertical sidewalls. In one embodiment, a liner layer is used as a hard mask in the production of the via and defines the position of the sections of the via.

Abstract: The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses.

Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.