Abstract: A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also relates to a method for producing aligning marks. During the method, a planarization is carried out before material is removed from an auxiliary indentation.

Abstract: A semiconductor device having contact surfaces of different heights electrically connected to conductors defined on one or more patterned metal planes and a method for fabricating the semiconductor device. In one embodiment, the semiconductor device comprises a substrate having a process surface; a first contact and a second contact arranged on the substrate, a second contact surface of the second contact being at a greater distance, in a substrate-normal direction, from the substrate than a first contact surface of the first contact; a first conductor disposed in a first patterned metal plane and electrically connected to the first contact surface; and a second conductor disposed in a second patterned metal plane and electrically connected to the second contact surface, wherein the second metal plane is disposed at a greater distance, in the substrate-normal direction, from the substrate than the first metal plane.

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

Abstract: A semiconductor device (10) includes a semiconductor component integrated in a semiconductor substrate and a conductive pad (110) arranged on top of the semiconductor device (10). The conductive pad is electrically connected with the semiconductor component. The pad is arranged for connecting the semiconductor device (10) externally. A dielectric material (310) is positioned between the conductive pad (110) and a buried conductive layer (20) of the semiconductor device. The dielectric material (310) comprises a stress blocking structure.

Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.

Abstract: A test structure can be used to determine the electrical loadability of contacts. This structure includes a first interconnect line and a second interconnect line arranged above the first interconnect line. A via electrically couples the first interconnect line to the second interconnect line. A plurality of additional conductive structures are arranged in a closely adjacent manner around the via. These additional structures lie in the same plane as either the first interconnect line or the second interconnect line.

Abstract: In a method of producing a capacitor in a first dielectric layer, a recess is formed in a surface of the first dielectric layer. On the surface of the first dielectric layer and in the recess a first conductive layer is formed. On the first conductive layer a second dielectric layer is formed, the sum of a thickness of the first conductive layer and of a thickness of the second dielectric layer in the recess being smaller than a depth of said recess. A second conductive layer is formed on the second dielectric layer. The capacitor is obtained by planarizing the thus formed layer structure.

Abstract: The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having an auxiliary structure side edge, wherein the useful structure side edge is opposite to the auxiliary structure side edge separated by a distance, and wherein the auxiliary structure useful structure distance is dimensioned such that a form of the useful structure side edge or a form of the substrate next to the useful structure side edge differs from a form in a device where there is no auxiliary structure.

Abstract: A semiconductor device having contact surfaces of different heights electrically connected to conductors defined on one or more patterned metal planes and a method for fabricating the semiconductor device. In one embodiment, the semiconductor device comprises a substrate having a process surface; a first contact and a second contact arranged on the substrate, a second contact surface of the second contact being at a greater distance, in a substrate-normal direction, from the substrate than a first contact surface of the first contact; a first conductor disposed in a first patterned metal plane and electrically connected to the first contact surface; and a second conductor disposed in a second patterned metal plane and electrically connected to the second contact surface, wherein the second metal plane is disposed at a greater distance, in the substrate-normal direction, from the substrate than the first metal plane.

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses.

Abstract: A test structure can be used to determine the electrical loadability of contacts. This structure includes a first interconnect line and a second interconnect line arranged above the first interconnect line. A via electrically couples the first interconnect line to the second interconnect line. A plurality of additional conductive structures are arranged in a closely adjacent manner around the via. These additional structures lie in the same plane as either the first interconnect line or the second interconnect line.