Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.

Abstract: Embodiments show a method for fabricating a cavity structure, a semiconductor structure, a cavity structure for a semiconductor device and a semiconductor microphone fabricated by the same. In some embodiments the method for fabricating a cavity structure comprises providing a first layer, depositing a carbon layer on the first layer, covering at least partially the carbon layer with a second layer to define the cavity structure, removing by means of dry etching the carbon layer between the first and second layer so that the cavity structure is formed.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

Abstract: Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.

Abstract: An integrated circuit includes a field effect transistor formed in an active area segment of a semiconductor substrate. The transistor comprises: a first source/drain contact region including a first vertical extension and a second source/drain contact region including a second vertical extension and a channel region formed around a recessed channel transistor groove, the groove being formed in the active area segment and extending to a groove depth larger than a lower first contact region depth, wherein the second vertical extension of the second source/drain contact region is arranged above the first extension of the first source/drain contact region, and wherein the recessed channel transistor groove is filled with a conductive gate material at a groove depth lower than the first contact region depth.

Abstract: A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.

Abstract: An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

Abstract: A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.

Abstract: An integrated circuit including an array of memory cells and method. In one embodiment, each memory cell includes a resistively switching memory element and a selection diode for selecting one cell from the plurality of memory cells. The memory element is coupled with its top to a first selection line and with its bottom side to the selection diode, the diode further being coupled to the bottom side of a second selection line.

Abstract: An integrated circuit on a substrate comprises a buffer capacitor in a buffer region. The buffer capacitor comprises a buffer electrode arranged at least partially in a recess, and a dielectric layer disposed between the buffer electrode and the substrate.

Abstract: An integrated circuit includes an array of diodes and an electrode coupled to each diode. The integrated circuit includes a layer of resistance changing material coupled to the electrodes and bit lines coupled to the layer of resistance changing material. The layer of resistance changing material provides a resistance changing element at each intersection of each electrode and each bit line.