Abstract: A device includes an array of memory cells, which are arranged vertically to a main substrate surface. The array is provided with lower bitlines, wordlines and upper bitlines. The lower and upper bitlines are contact-connected to lower source/drain regions and corresponding upper source/drain regions, respectively, in such a manner that a unique addressing of individual memory cells is possible.

Abstract: According to the invention, the method comprises the steps of: fabricating a first conductive layer including a first contact pad and covering the first conductive layer with a first protection layer at least on top of the first contact pad such that a first protective cap is formed thereon; fabricating a second conductive layer including a second contact pad, wherein the second conductive layer and the first conductive layer are electrically insulated from one another, and covering the second conductive layer with a second protection layer at least on top of the second contact pad such that a second protective cap is formed thereon; depositing at least one intermediate layer on top of the structure; forming a mask on top of the intermediate layer and etching the intermediate layer thereby exposing the first protective cap and the second protective cap, wherein an etchant is applied that provides a larger etch rate with regard to the intermediate layer than with regard to the protective layer; and after expos

Abstract: A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

Abstract: Fabrication of recessed channel array transistors (RCAT) with a corner gate device includes forming pockets between a semiconductor fin that includes a gate groove and neighboring shallow trench isolations that extend along longs sides of the semiconductor fin. A protection liner covers the semiconductor fin and the trench isolations in a bottom portion of the gate groove and the pockets. An insulator collar is formed in the exposed upper sections of the gate groove and the pockets, wherein a lower edge of the insulator collar corresponds to a lower edge of source/drain regions formed within the semiconductor fin. The protection liner is removed. The bottom portion of the gate groove and the pockets are covered with a gate dielectric and a buried gate conductor layer. The protection liner avoids residuals of polycrystalline silicon between the active area in the semiconductor fin and the insulator collar.

Abstract: The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.

Abstract: A semiconductor substrate is provided comprising a plurality of contact pads arranged on a horizontal surface of the semiconductor substrate. Pillars of a first sacrificial material are formed on the contact pads. A first dielectric layer is deposited thus covering at least said pillars. A first conductive layer is deposited between said pillars covered with the first dielectric layer. The pillars are removed thus providing trenches in the first conductive layer having walls covered with the dielectric layer. A second conductive layer is deposited on the first dielectric layer in the trench. A second dielectric layer is deposited such that at least the second conductive layer in the trench is covered by the second dielectric layer. A third conductive layer is deposited on the second dielectric layer.

Abstract: A method for fabricating a contact structure for a stack storage capacitor includes forming the contact structure in a node contact region with contact openings, an insulating liner and a conductive filling material prior to the patterning of bit lines.

Abstract: A memory device includes an array of memory cells and a storage capacitor for storing information. Each memory cell includes an access transistor. The access transistor includes first and second source/drain regions, a channel disposed between the first and the second source/drain regions, and a gate electrode electrically insulated from the channel and adapted to control the conductivity of the channel. The access transistor is at least partially formed in the semiconductor substrate. The storage capacitor is adapted to be accessed by the access transistor. The storage capacitor includes at least first and second storage electrodes and at least a capacitor dielectric disposed between the first and the second storage electrodes. Each of the first and the second storage electrodes is disposed above the substrate surface.

Abstract: A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.