Abstract: An apparatus is described. The apparatus includes peer-to-peer intelligence to be integrated into a mass storage system having a cache and a backing store. The peer-to-peer intelligence is to move data between the cache and backing store without the data passing through main memory.

Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

Abstract: An apparatus is described. The apparatus includes peer-to-peer intelligence to be integrated into a mass storage system having a cache and a backing store. The peer-to-peer intelligence is to move data between the cache and backing store without the data passing through main memory.

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Abstract: Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space.

Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.

Abstract: Provided are an apparatus and method for persisting blocks of data and metadata in a non-volatile memory (NVM) cache. A non-volatile memory (NVM) cache caches blocks of data from the storage of the first block size and metadata for each of the cached blocks of data indicating a status of the cached block of data, including whether the block of data is modified or unmodified, and a location in the storage where the block of data is stored. The non-volatile memory has blocks of a second block size greater than the first block size, wherein one of the blocks in the non-volatile memory stores the block of data from the storage and the metadata for the block of data. A cache manager writes the block of data and the metadata for the block of data to one of the blocks in the non-volatile memory cache and writes the block of data in one of the blocks in the non-volatile memory cache to the storage.

Abstract: Technologies for enhanced memory wear leveling is disclosed. In the illustrative embodiment, a storage controller on a storage sled performs wear leveling across several storage devices. For example, the storage controller may copy hot data from one storage device that has a high number of erasures to another storage device that has a lower number of erasures in order to make the number of erasures between the devices more even by accumulating further erasures associated with the hot data on the drive that has the lower number of erasures.

Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.

Abstract: Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space.

Abstract: A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.

Abstract: A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.

Abstract: Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space.

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Abstract: A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage.

Abstract: Technologies for establishing and managing a high-performance memory region of a solid state drive include reserving a region of a volatile memory of the solid state drive for storage of host data. Memory accesses received from a host may be directed toward the reserved region of the volatile memory or toward a non-volatile memory of the solid state drive. Due to the structure of the volatile memory, memory accesses to the reserved region may exhibit lower access timing relative to memory accesses to the non-volatile memory. As such, the reserved region may be utilized as storage space for journaling and logging of data and/or other applications. Upon shutdown or a power failure event, data stored in the reserved region of the volatile memory is copied to the non-volatile memory and subsequently reinstated to the volatile memory upon the next initialization event.

Abstract: Methods and apparatus related to efficient Solid State Drive (SSD) data compression scheme and layout are described. In one embodiment, logic, coupled to non-volatile memory, receives data (e.g., from a host) and compresses the data to generate compressed data prior to storage of the compressed data in the non-volatile memory. The compressed data includes a compressed version of the data, size of the compressed data, common meta information, and final meta information. Other embodiments are also disclosed and claimed.

Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.

Abstract: The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies.