Patents by Inventor Ko-Cheng Liu
Ko-Cheng Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250254123Abstract: A load balancing system and method is provided. The load balancing system includes a core network, CPEs (customer premise equipments), user equipments, and a load balancing equipment. The CPEs receive signals from the core network and connect to each other through a network topology. The user equipments are connected to the CPEs. The load balancing equipment is connected to one CPE, and the load balancing equipment confirms a throughput limit of each CPE and includes a data analysis module and a processing unit. The data analysis module receives network parameters between the CPEs and the user equipments, and calculates premise throughputs of the CPEs. The processing unit generates a route control table according to the premise throughputs. According to the route control table, the CPEs adjusts signal transmission between the CPEs and the user equipments to balance the premise throughputs of the CPEs.Type: ApplicationFiled: May 7, 2024Publication date: August 7, 2025Inventors: Ching-Yu Chen, Yi-Ching Chen, Ko-Cheng Liu
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Publication number: 20250203949Abstract: A semiconductor structure includes a substrate including a dielectric layer over a semiconductor layer and an active region protruding from the dielectric layer. The active region includes a stack of semiconductor layers. The semiconductor structure further includes a metal gate structure disposed over the active region and interleaved with the stack of semiconductor layers, an isolation structure over the dielectric layer and covering sidewalls of a bottommost semiconductor layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the metal gate structure. A bottom surface of the epitaxial S/D feature is defined by the bottommost semiconductor layer, and a portion of the bottommost semiconductor layer under the epitaxial S/D feature has a thickness less than a thickness of the dielectric layer.Type: ApplicationFiled: February 17, 2025Publication date: June 19, 2025Inventors: Wei-Lun Min, Ko-Cheng Liu, Chang-Miao Liu
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Patent number: 12324218Abstract: A method includes providing a semiconductor structure including a device fin protruding from a substrate, forming a dummy gate stack over the device fin, forming a first spacer over the device fin and the dummy gate stack, forming a second spacer over the first spacer, forming a dielectric feature adjacent to the second spacer, and replacing the dummy gate stack with a metal gate stack. Thereafter, the method removes the second spacer, thereby forming an air gap between the first spacer and the dielectric feature and wrapping around the device fin. The method then forms a sealing layer over the first spacer and the dielectric feature, thereby sealing the air gap.Type: GrantFiled: July 20, 2021Date of Patent: June 3, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
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Patent number: 12278276Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.Type: GrantFiled: August 30, 2021Date of Patent: April 15, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
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Patent number: 12230720Abstract: A method includes providing a substrate including a first semiconductor layer over a dielectric layer, thinning the first semiconductor layer, forming a stack of alternating second semiconductor layers and third semiconductor layers over the thinned first semiconductor layer, forming a fin active region protruding from the substrate including a portion of the thinned first semiconductor layer and the stack of alternating second semiconductor layers and third semiconductor layers, forming isolation features over an exposed portion of the dielectric layer, forming a dummy gate stack over the fin active region, forming a source/drain (S/D) recess in the fin active region adjacent to the dummy gate stack, forming an epitaxial S/D feature in the S/D recess, removing the second semiconductor layers to form openings between the third semiconductor layers, and forming a metal gate stack in the openings and in place of the dummy gate stack.Type: GrantFiled: August 30, 2021Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Lun Min, Ko-Cheng Liu, Chang-Miao Liu
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Patent number: 12183806Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes providing a workpiece having a first active region and a second active region protruding from a substrate, lined by cladding layers, and spaced by a first trench. The method also includes forming a dielectric layer over the workpiece to substantially fill the first trench, forming a mask film directly on a portion of the dielectric layer in the first trench after the forming of the dielectric layer, selectively recessing the dielectric layer after the forming of the mask film to form a dummy fin in and protruding from the first trench, performing an etching process to selectively remove the cladding layers to form second trenches, and forming a gate structure over the workpiece to fill the second trenches.Type: GrantFiled: April 28, 2022Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Chang-Miao Liu
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Patent number: 12166071Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.Type: GrantFiled: August 10, 2022Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20240379816Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a diffusion blocking layer on a semiconductor substrate; forming channel material layers over the diffusion blocking layer; patterning the semiconductor substrate, the channel material layers, and the diffusion blocking layer to form a trench in the semiconductor substrate, thereby defining an active region being adjacent the trench; filling the trench with a dielectric material layer and a solid doping source material layer containing a dopant; and driving the dopant from the solid doping source material layer to the active region, thereby forming an anti-punch-through (APT) feature in the active region.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
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Publication number: 20240379813Abstract: A semiconductor structure includes a substrate, a semiconductor fin-shaped structure protruding from the substrate and extending lengthwise along a first direction, an isolation feature disposed over the substrate and adjacent to the semiconductor fin-shaped structure and extending lengthwise along the first direction, a metal gate stack disposed over a channel region of the semiconductor fin-shaped structure and extending lengthwise along a second direction perpendicular to the first direction, a gate spacer disposed along a sidewall of the metal gate stack and along a sidewall of the semiconductor fin-shaped structure, a source/drain feature disposed over a source/drain region of the semiconductor fin-shaped structure and adjacent to the metal gate stack, a dielectric layer disposed over the source/drain feature, and an air gap disposed between the gate spacer and the dielectric layer along the first direction and wrapping around the semiconductor fin-shaped structure.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20240379744Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Ko-Cheng Liu, Ming-Shuan Li, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20240339362Abstract: Semiconductor structures and methods are provided. In an embodiment, a semiconductor structure includes a substrate including a first mesa structure and a second mesa structure, an isolation feature extending between the first mesa structure and the second mesa structure, a first vertical stack of nanostructures directly over the first mesa structure, first source/drain features coupled to the first vertical stack of nanostructures, a dielectric layer comprising a first portion disposed on the isolation feature and a second portion disposed between the first-type source/drain features and the substrate, and a first gate structure wrapping around each nanostructure of the first vertical stack of nanostructures.Type: ApplicationFiled: April 4, 2023Publication date: October 10, 2024Inventors: Ko-Cheng Liu, Chang-Miao Liu, Huiling Shang
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Publication number: 20240162331Abstract: The present disclosure provides a method that includes forming a stack including first and second semiconductor layers over a semiconductor substrate, the first and second semiconductor layers having different material compositions and alternating with one another within the stack; forming a dummy gate structure over the stack, the dummy gate structure wrapping around top and sidewall surfaces of the stack; forming a gate spacer on sidewalls of the dummy gate structure and disposed on the top of the stack; forming a dielectric layer with the dummy gate embedded therein; removing the dummy gate structure, resulting in a gate trench; removing the second semiconductor layers through the gate trench such that the first semiconductor layers form semiconductor sheets; forming a metal gate wrapping around the semiconductor sheets; and thereafter, forming a source/drain feature adjacent the metal gate and connecting to the semiconductor sheets.Type: ApplicationFiled: January 20, 2023Publication date: May 16, 2024Inventors: Ko-Cheng Liu, Chang-Miao Liu
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Publication number: 20240113198Abstract: A method of fabricating a device includes providing a plurality of fins extending from a substrate. In some embodiments, each fin of the plurality of fins includes a plurality of semiconductor channel layers. In various example, the method further includes performing an ion implantation process into a first fin of the plurality of fins to introduce a dopant species into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin. In some embodiments, the ion implantation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin.Type: ApplicationFiled: January 19, 2023Publication date: April 4, 2024Inventors: Ko-Cheng LIU, Chang-Miao LIU
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Publication number: 20230395681Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a cladding layer on sidewalls of the semiconductor fin, forming first and second dielectric fins sandwiching the semiconductor fin, and removing the cladding layer. The removal of the cladding layer forms trenches between the semiconductor fin and the first and second dielectric fins. After the removing of the cladding layer, a dummy gate structure is formed over the semiconductor fin and in the trenches. The method also includes recessing the semiconductor fin in a region proximal to the dummy gate structure, forming an epitaxial feature on the recessed semiconductor fin, and forming a metal gate stack replacing the dummy gate structure. A top surface of the recessed semiconductor fin in the region has a concave shape.Type: ApplicationFiled: June 5, 2022Publication date: December 7, 2023Inventors: Ko-Cheng Liu, Chang-Miao Liu, Huiling Shang
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Patent number: 11837631Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.Type: GrantFiled: April 9, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20230387198Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate, a dielectric fin disposed adjacent and substantially parallel to the semiconductor fin, an epitaxial source/drain (S/D) feature disposed in the semiconductor fin, a dielectric layer disposed between a sidewall of the epitaxial S/D feature and a sidewall of the dielectric fin, and an air gap disposed in the dielectric layer.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20230352560Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary method includes providing a workpiece having a first active region and a second active region protruding from a substrate, lined by cladding layers, and spaced by a first trench. The method also includes forming a dielectric layer over the workpiece to substantially fill the first trench, forming a mask film directly on a portion of the dielectric layer in the first trench after the forming of the dielectric layer, selectively recessing the dielectric layer after the forming of the mask film to form a dummy fin in and protruding from the first trench, performing an etching process to selectively remove the cladding layers to form second trenches, and forming a gate structure over the workpiece to fill the second trenches.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Ko-Cheng Liu, Chang-Miao Liu
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Publication number: 20230352530Abstract: The method includes receiving a semiconductor workpiece having active regions extending above a top surface of a semiconductor substrate, forming first dielectric features on first opposing sidewalls of the active regions across a first direction, forming second dielectric features extending between opposing sidewalls of the first dielectric features, and etching portions of the active region to form source/drain trenches. The source/drain trenches expose second opposing sidewalls of the active region. The method further includes recessing the first dielectric features and forming source/drain features in the source/drain trenches and on the exposed second opposing sidewalls of the active region. The source/drain features are partially formed on top surfaces of the first dielectric features.Type: ApplicationFiled: June 26, 2023Publication date: November 2, 2023Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu
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Publication number: 20230261077Abstract: An exemplary device includes a stack of channel layers over a substrate extension, a gate, and an insulation layer. The stack of channel layers extends between a first epitaxial source/drain and a second epitaxial source/drain. The gate surrounds each channel layer of the stack of the channel layers. The insulation layer is over the substrate extension, the gate is between a bottommost channel layer of the stack of channel layers and the insulation layer, and the insulation layer is between the gate and the substrate extension. The insulation layer extends between the first epitaxial source/drain and the second epitaxial source/drain, each of which may include an undoped epitaxial layer. A top surface of the undoped epitaxial layer is below a bottom surface of the bottommost channel layer and/or above a top surface of the insulation layer. The insulation layer may wrap the substrate extension and/or have an air gap therein.Type: ApplicationFiled: June 6, 2022Publication date: August 17, 2023Inventors: Ko-Cheng Liu, Chang-Miao Liu, Ming-Lung Cheng
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Patent number: 11688768Abstract: The device includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to the substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure that engages with the stack of channel layers and extending along a first direction. Additionally, the device includes a source/drain feature on first sidewall surfaces of the stack of channel layers and on the substrate, where the first sidewall surfaces extends in parallel to the first direction. Moreover, the source/drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.Type: GrantFiled: March 5, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ko-Cheng Liu, Ming-Lung Cheng, Chang-Miao Liu