Patents by Inventor Ko-Min Chang
Ko-Min Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10095186Abstract: A wrist watch and method of activating a user interface of the wrist watch are described. The wrist watch comprises a display for providing a user interface for a user when wearing the wrist watch on a wrist, a first motion sensor arranged to detect motion of the wrist watch and a proximity detector arranged to detect the proximity of a hand of the user when wearing the wrist watch. A data processor is configured to activate the user interface when the first motion sensor detects that the wrist of the user has been raised and the proximity detector detects that the hand of the user has moved toward the wrist watch.Type: GrantFiled: September 8, 2017Date of Patent: October 9, 2018Assignee: NXP B.V.Inventors: Arjen Helder, Ko-Min Chang, Sammy Geeraerts
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Publication number: 20180074462Abstract: A wrist watch and method of activating a user interface of the wrist watch are described. The wrist watch comprises a display for providing a user interface for a user when wearing the wrist watch on a wrist, a first motion sensor arranged to detect motion of the wrist watch and a proximity detector arranged to detect the proximity of a hand of the user when wearing the wrist watch. A data processor is configured to activate the user interface when the first motion sensor detects that the wrist of the user has been raised and the proximity detector detects that the hand of the user has moved toward the wrist watch.Type: ApplicationFiled: September 8, 2017Publication date: March 15, 2018Inventors: Arjen Helder, Ko-Min Chang, Sammy Geeraerts
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Patent number: 9620604Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.Type: GrantFiled: February 3, 2016Date of Patent: April 11, 2017Assignee: NXP USA, INC.Inventors: Anirban Roy, Ko-Min Chang
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Patent number: 9425055Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.Type: GrantFiled: May 28, 2014Date of Patent: August 23, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Ko-Min Chang, Craig T. Swift
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Publication number: 20160155813Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.Type: ApplicationFiled: February 3, 2016Publication date: June 2, 2016Inventors: Anirban Roy, Ko-Min Chang
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Patent number: 9318501Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.Type: GrantFiled: June 12, 2014Date of Patent: April 19, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Anirban Roy, Ko-Min Chang
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Publication number: 20150364478Abstract: A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: Anirban ROY, Ko-Min CHANG
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Publication number: 20150349142Abstract: A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.Type: ApplicationFiled: May 28, 2014Publication date: December 3, 2015Inventors: BRIAN A. WINSTEAD, Ko-Min Chang, Craig T. Swift
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Patent number: 9136360Abstract: Forming a memory structure includes forming a charge storage layer over a substrate; forming a first control gate layer; patterning the first control gate layer to form an opening in the first control gate layer and the charge storage layer, wherein the opening extends into the substrate; filling the opening with an insulating material; forming a second control gate layer over the patterned first control gate layer and the insulating material; patterning the second control gate layer to form a first control gate electrode and a second control gate electrode, wherein the first control gate electrode comprises a first portion of each of the first and second control gate layers and the second control gate electrode comprises a second portion of each of the first and second control gate layers, and the insulating material is between the control gate electrodes; and forming select gate electrodes adjacent the control gate electrodes.Type: GrantFiled: June 6, 2014Date of Patent: September 15, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Asanga H. Perera, Ko-Min Chang, Craig T. Swift
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Patent number: 9114980Abstract: A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.Type: GrantFiled: June 1, 2012Date of Patent: August 25, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
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Patent number: 9118008Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: GrantFiled: June 11, 2014Date of Patent: August 25, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
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Patent number: 8962385Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer includes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.Type: GrantFiled: September 18, 2014Date of Patent: February 24, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Cheong M. Hong, Ko-Min Chang, Feng Zhou
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Publication number: 20150004747Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer includes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.Type: ApplicationFiled: September 18, 2014Publication date: January 1, 2015Inventors: CHEONG M. HONG, KO-MIN CHANG, FENG ZHOU
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Patent number: 8921155Abstract: A resistive random access memory cell uses a substrate and includes a gate stack over the substrate. The gate stack includes a first copper layer over the substrate, a copper oxide layer over the first copper layer, and a second copper layer over the copper oxide layer.Type: GrantFiled: April 12, 2011Date of Patent: December 30, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Feng Zhou, Ko-Min Chang, Cheong Min Hong
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Patent number: 8860001Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.Type: GrantFiled: April 9, 2012Date of Patent: October 14, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Cheong Min Hong, Ko-Min Chang, Feng Zhou
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Publication number: 20140295639Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: ApplicationFiled: June 11, 2014Publication date: October 2, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: FENG ZHOU, Frank K. Baker, JR., Ko-Min Chang, Cheong Min Hong
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Patent number: 8835295Abstract: A method for forming a split gate device includes forming a first sidewall of a first conductive gate layer, wherein the semiconductor layer includes a tunnel region laterally adjacent the first sidewall, forming a dielectric layer along the first sidewall to provide for increased thickness of a gap spacer, forming a charge storage layer over a portion of a top surface of the first conductive layer and over the tunnel region, and forming a second conductive gate layer over the charge storage layer.Type: GrantFiled: August 7, 2013Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jinmiao J. Shen, Ko-Min Chang, Brian A. Winstead
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Patent number: 8779405Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: GrantFiled: June 1, 2012Date of Patent: July 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
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Publication number: 20130320285Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Inventors: Feng Zhou, Frank K. Baker, JR., Ko-Min Chang, Cheong Min Hong
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Publication number: 20130320284Abstract: A resistive random access memory (ReRAM) cell, comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and an interface region comprising a plurality of interspersed field focusing features that are not photo-lithographically defined. The interface region is located between the first conductive electrode and the dielectric storage material layer or between the dielectric storage material layer and the second conductive electrode.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Inventors: Feng Zhou, Frank K. Baker, JR., Ko-Min Chang, Cheong Min Hong