Abstract: A cross-point EEPROM memory array includes a semiconductor substrate (10) having first and second bit-lines (32, 34) spaced apart by a channel region (36). A control gate electrode (24) is formed by a portion of a control gate line, which overlies a first portion of the channel region (36) and is separated therefrom by an ONO layer (17). A select gate electrode (40) is formed by a portion of a select gate line disposed on the substrate (10) perpendicular to the control gate line. Individual cells in the array are programmed by injecting electrons using source-side injection into trapping sites (19) in the silicon nitride layer (14) of the ONO layer (17). The cells in the array are erased by electron tunneling through the top silicon dioxide layer (16) of the ONO layer (17), and are dissipated in the control gate electrode (24).

Abstract: A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.

Abstract: A flash EEPROM array (22) is erased and a threshold voltage distribution of the erased flash EEPROM cells (36, 39-46) is converged to within a predetermined voltage range by using a two-step erasing procedure. In the first step, flash EEPROM array (22) is electrically bulk erased using a conventional bulk erase procedure. Electrons are tunneled from the floating gate (38) to the source, causing cells (36, 39-46) to have a relatively low threshold voltage. In the second step, the threshold voltage distribution of the array (22) is converged to within the predetermined voltage range by grounding the source and drain of each cell (36, 39-46), while concurrently applying a high positive voltage to the control gate (27) of each cell (36, 39-46). Some electrons are tunneled back to the floating gate (38), thus converging the threshold voltage distribution to within a predetermined range.

Abstract: An EEPROM cell (10) has a tunnel opening (28) which overlaps both an active region (12) and field isolation regions (14). A tunnel area (30), which is that portion of the cell in which electrons tunnel through a tunnel dielectric (32) to charge or discharge a floating gate (22) during device operation, is defined as the overlapped portion of the tunnel opening (28) and the active region (12). By having the tunnel opening (28) larger than the tunnel area (30), etch processes used to pattern the opening in a gate dielectric (26) are more easily controlled and the active region area beneath the floating gate is reduced. The EEPROM cell (10) has a tunnel area which is limited in size by lithographic resolution capabilities rather than by limitations in dielectric etch processes. The tunnel features increase a capacitance coupling ratio of the cell.

Abstract: Programming speed of a nonvolatile memory is improved by enhancing carrier generation. In one form, a nonvolatile memory has a control gate which overlies a channel region in a substrate. A floating gate overlies a portion of the channel region and is positioned between the substrate and the control gate. A source and a drain are formed in the substrate, being displaced by the channel region. A first programming voltage is applied to the drain to create an electric field at a junction between the drain and channel region. Current is forced into the source and through the substrate in order to enhance carrier generation at the junction between the drain and channel region, thereby increasing an electric field at the junction. A second programming voltage, having a ramp shaped leading edge, is applied to the control gate to increase the electrical field and to program the memory to a predetermined logic state.

Abstract: A floating gate is utilized which has two portions. A first portion overlies the channel region formed between the source and drain. The control gate overlies this portion of the floating gate and the remaining portion of the channel region forming an enhancement transistor. The second portion of the floating gate extends from the first portion over a thin oxide tunnel area of the source. An additional diode implant forming a junction with the drain region is provided to regulate the current flow through the drain, particularly during erasure.

Abstract: Zener diodes that are formed concurrently with flash EEPROM cells are utilized to regulate programming voltages for programming a flash EEPROM cell (37). A selected bit-line (38) is voltage regulated with both a zener diode (19) and a bias transistor (36). The bias transistor is activated during programming to prevent breaking down a drain junction of a flash EEPROM cell, which would generate hot-electrons and cause a runaway programming problem. The regulated voltage on the bit-line is also utilized to optimize programming characteristics of a flash EEPROM cell, and to minimize disturbing a programmed logic state of flash EEPROM cells connected to a commonly selected bit-line. A separate zener diode (17) provides a regulated voltage for a selected word-line (40) during programming. By regulating the voltage of the word-line during programming, a program disturb problem associated with a high voltage word-line is minimized.