Patents by Inventor Ko Miyazaki

Ko Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6596656
    Abstract: A method is provided for well printing a specified pattern even when the exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm. When exposure treatment is applied to a semiconductor wafer by using exposure light with a wavelength over 200 nm, a photomask is used. The photomask is provided with an opaque pattern of a resist layer on an organic layer which is photoabsorptive in reaction to exposure light.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: July 22, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Tanaka, Norio Hasegawa, Kazutaka Mori, Ko Miyazaki, Tsuneo Terasawa
  • Publication number: 20030109126
    Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.
    Type: Application
    Filed: November 25, 2002
    Publication date: June 12, 2003
    Inventors: Tsuneo Terasawa, Toshihiko Tanaka, Ko Miyazaki, Norio Hasegawa, Kazutaka Mori
  • Publication number: 20020078430
    Abstract: In a method of manufacturing a semiconductor integrated circuit capable of making gate electrode patterns of MOS transistors accurately in compliance with design data, exposure masks of the gate electrode patterns have the prior rendition of pattern shape assessment based on optical simulation. The assessment is carried out by optical simulation of a gate electrode pattern based on pattern data of layout design of the semiconductor integrated circuit. The model-based correction is applied to the optical simulation for the pattern shape assessment(S21-23). The model for the pattern shape assessment is formed by comparing test patterns with light intensity(S14) and defines compensation values correlative to dimensional differences of the light intensity patterns from the test patterns (S15). The test patterns are formed on a basis of test pattern data above different underlays on a test wafer and the light intensity patterns are formed by optical simulation based on test pattern data.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 20, 2002
    Inventor: Ko Miyazaki
  • Publication number: 20020052122
    Abstract: Well printing a specified pattern even when exposure treatment using a resist mask uses exposure light with a wavelength over 200 nm.
    Type: Application
    Filed: August 20, 2001
    Publication date: May 2, 2002
    Inventors: Toshihiko Tanaka, Norio Hasegawa, Kazutaka Mori, Ko Miyazaki, Tsuneo Terasawa
  • Publication number: 20020042007
    Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises properly using a photomask having light blocking patterns made of a metal and another photomask having light blocking patterns made of a resist film upon exposure treatment, depending on the fabrication step of the semiconductor integrated circuit device.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 11, 2002
    Inventors: Ko Miyazaki, Kazutaka Mori, Norio Hasegawa, Tsuneo Terasawa, Toshihiko Tanaka
  • Publication number: 20020032894
    Abstract: The optimization algorithm candidate of a plurality of circuit blocks given with the logic circuit description based on the hardware description language is determined considering the Hamming distance of circuit block (S1 to S3). The common circuit blocks of the optimization algorithm candidate determined in the first process are then grouped considering the coupling degree among circuit blocks (S4 to S6). Result of grouping is the result for the circuit blocks having apparent characteristic in the algorithm candidate and coupling degree and the circuit blocks having uncertain characteristics are also left. In view of optimizing the grouping for the circuit blocks having uncertain characteristics, the grouping of a plurality of circuit blocks is optimized with the hereditary algorithm by reflecting the result of grouping on the initial condition.
    Type: Application
    Filed: August 6, 2001
    Publication date: March 14, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Ko Miyazaki, Kazuhiko Eguchi, Tadaaki Tanimoto
  • Publication number: 20020006555
    Abstract: In order to shorten the time required to change or correct a mask pattern over a mask, light-shielding patterns formed of a resist film for integrated circuit pattern transfer are partly provided over a mask substrate constituting a photomask in addition to light-shielding patterns formed of a metal for the integrated circuit pattern transfer.
    Type: Application
    Filed: June 18, 2001
    Publication date: January 17, 2002
    Inventors: Norio Hasegawa, Toshihiko Tanaka, Joji Okada, Kazutaka Mori, Ko Miyazaki
  • Patent number: 5159664
    Abstract: A graphic processor comprises an input device for inputting a command from an operator, a display device for displaying graphic data and a computer for preparing and correcting graphic data by a command input from the operator and for making display control of the display device. When the operator wants to know the content of the command that is executed, he instructs the command to the computer. A command name, a processing content and a figure as an object of processing are calculated from history data instructed from the computer. The figure as the object of processing, the command processing content and the relation of correspondence are symbolized and displayed on the display device. Furthermore, a parametric figure is also displayed visually on the display device.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: October 27, 1992
    Assignees: Hitachi Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Tetsuya Yamamoto, Goro Suzuki, Susumu Sugawara, Nobuhiro Hamada, Ko Miyazaki, Tsuyoshi Takahashi, Susumu Tamura, Mikihiko Motoki