Patents by Inventor Kohei Choraku
Kohei Choraku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11749874Abstract: A balanced-type circular disk resonator includes a circular conductive layer, a conductive member including a first conductive portion provided on a first surface of the circular conductive layer to enable a first dielectric board, a dielectric property of which is measured, to be placed between the first conductive portion and the circular conductive layer, and a second conductive portion provided on a second surface of the circular conductive layer to enable a second dielectric board, a dielectric property of which is measured, to be placed between the second conductive portion and the circular conductive layer, the second surface being opposite to the first surface with regard to the circular conductive layer, and a temperature adjustment unit coupled to the conductive member and configured to adjust temperatures of the first conductive portion and the second conductive portion.Type: GrantFiled: March 24, 2021Date of Patent: September 5, 2023Assignee: FUJITSU LIMITEDInventors: Kohei Choraku, Yoshiyuki Hiroshima
-
Patent number: 11435385Abstract: A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency f1 that is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t1, and an unloaded Qu1 that corresponds to the resonance frequency f1; performing second measurement to obtain a resonance frequency f2 that is outputted to the measuring device when the first and second dielectric flat plates each have a thickness t2 that is different from the thickness t1, and an unloaded Qu2 that corresponds to the resonance frequency f2; and calculating a specific conductivity ?r of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Qu1, the resonance frequency f2, and the unloaded Qu2.Type: GrantFiled: April 16, 2020Date of Patent: September 6, 2022Assignee: FUJITSU LIMITEDInventors: Kazuki Takahashi, Akiko Matsui, Kohei Choraku, Mitsunori Abe, Tetsuro Yamada, Yoshio Kobayashi, Sotaro Kobayashi
-
Publication number: 20210367315Abstract: A balanced-type circular disk resonator includes a circular conductive layer, a conductive member including a first conductive portion provided on a first surface of the circular conductive layer to enable a first dielectric board, a dielectric property of which is measured, to be placed between the first conductive portion and the circular conductive layer, and a second conductive portion provided on a second surface of the circular conductive layer to enable a second dielectric board, a dielectric property of which is measured, to be placed between the second conductive portion and the circular conductive layer, the second surface being opposite to the first surface with regard to the circular conductive layer, and a temperature adjustment unit coupled to the conductive member and configured to adjust temperatures of the first conductive portion and the second conductive portion.Type: ApplicationFiled: March 24, 2021Publication date: November 25, 2021Applicant: FUJITSU LIMITEDInventors: Kohei Choraku, YOSHIYUKI HIROSHIMA
-
Patent number: 11158964Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.Type: GrantFiled: June 8, 2020Date of Patent: October 26, 2021Assignee: FUJITSU LIMITEDInventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, Yoshiyuki Hiroshima, Kohei Choraku, Kazuki Takahashi, Akiko Matsui, Shigeo Iriguchi
-
Patent number: 10877216Abstract: An optical waveguide substrate includes a substrate that includes a recess, a buffer layer disposed on a bottom surface and a wall surface of the recess, and an optical waveguide disposed inside the recess with the buffer layer interposed therebetween and having a cladding layer disposed on the buffer layer and a core layer disposed inside the cladding layer.Type: GrantFiled: April 9, 2019Date of Patent: December 29, 2020Assignee: FUJITSU LIMITEDInventors: Kohei Choraku, Akiko Matsui, Yoshiyuki Hiroshima, Kazuki Takahashi, Tetsuro Yamada
-
Publication number: 20200341042Abstract: A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency f1 that is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t1, and an unloaded Qu1 that corresponds to the resonance frequency f1; performing second measurement to obtain a resonance frequency f2 that is outputted to the measuring device when the first and second dielectric flat plates each have a thickness t2 that is different from the thickness t1, and an unloaded Qu2 that corresponds to the resonance frequency f2; and calculating a specific conductivity ?r of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Qu1, the resonance frequency f2, and the unloaded Qu2.Type: ApplicationFiled: April 16, 2020Publication date: October 29, 2020Applicant: FUJITSU LIMITEDInventors: Kazuki TAKAHASHI, AKIKO MATSUI, Kohei Choraku, Mitsunori Abe, Tetsuro Yamada, Yoshio Kobayashi, Sotaro Kobayashi
-
Publication number: 20200303849Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.Type: ApplicationFiled: June 8, 2020Publication date: September 24, 2020Applicant: FUJITSU LIMITEDInventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, YOSHIYUKI HIROSHIMA, Kohei Choraku, Kazuki TAKAHASHI, AKIKO MATSUI, Shigeo Iriguchi
-
Patent number: 10714849Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.Type: GrantFiled: February 1, 2019Date of Patent: July 14, 2020Assignee: FUJITSU LIMITEDInventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, Yoshiyuki Hiroshima, Kohei Choraku, Kazuki Takahashi, Akiko Matsui, Shigeo Iriguchi
-
Patent number: 10492291Abstract: A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.Type: GrantFiled: March 22, 2017Date of Patent: November 26, 2019Assignee: FUJITSU LIMITEDInventors: Yoshiyuki Hiroshima, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
-
Publication number: 20190324207Abstract: An optical waveguide substrate includes a substrate that includes a recess, a buffer layer disposed on a bottom surface and a wall surface of the recess, and an optical waveguide disposed inside the recess with the buffer layer interposed therebetween and having a cladding layer disposed on the buffer layer and a core layer disposed inside the cladding layer.Type: ApplicationFiled: April 9, 2019Publication date: October 24, 2019Applicant: FUJITSU LIMITEDInventors: Kohei Choraku, AKIKO MATSUI, YOSHIYUKI HIROSHIMA, Kazuki TAKAHASHI, Tetsuro Yamada
-
Publication number: 20190245284Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.Type: ApplicationFiled: February 1, 2019Publication date: August 8, 2019Applicant: FUJITSU LIMITEDInventors: Takahide Mukoyama, Tetsuro Yamada, Mitsuhiko Sugane, YOSHIYUKI HIROSHIMA, Kohei Choraku, Kazuki TAKAHASHI, AKIKO MATSUI, Shigeo Iriguchi
-
Patent number: 10353158Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.Type: GrantFiled: November 15, 2017Date of Patent: July 16, 2019Assignee: FUJITSU LIMITEDInventors: Yoshiyuki Hiroshima, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
-
Patent number: 10212805Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.Type: GrantFiled: November 9, 2017Date of Patent: February 19, 2019Assignee: FUJITSU LIMITEDInventors: Tetsuro Yamada, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Yoshiyuki Hiroshima, Kohei Choraku
-
Patent number: 10164312Abstract: A wiring board includes: a first substrate that includes signal wiring; a second substrate that includes a conductor with an area larger than an area of the signal wiring, and projection formed on a face of the conductor and constituted of an insulator with a pattern corresponding to a pattern of the signal wiring, the second substrate being arranged so that the face of the conductor on which the projection is formed faces the signal wiring; and an intermediate layer that is arranged between the signal wiring and the conductor and includes a fibrous member.Type: GrantFiled: August 10, 2016Date of Patent: December 25, 2018Assignee: FUJITSU LIMITEDInventors: Tetsuro Yamada, Akiko Matsui, Mitsuhiko Sugane, Takahide Mukoyama, Yoshiyuki Hiroshima, Kohei Choraku
-
Patent number: 10151878Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.Type: GrantFiled: June 19, 2017Date of Patent: December 11, 2018Assignee: FUJITSU LIMITEDInventors: Kohei Choraku, Akiko Matsui, Tetsuro Yamada, Yoshiyuki Hiroshima
-
Publication number: 20180184514Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.Type: ApplicationFiled: November 9, 2017Publication date: June 28, 2018Applicant: FUJITSU LIMITEDInventors: Tetsuro Yamada, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, YOSHIYUKI HIROSHIMA, Kohei Choraku
-
Publication number: 20180156993Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.Type: ApplicationFiled: November 15, 2017Publication date: June 7, 2018Applicant: FUJITSU LIMITEDInventors: YOSHIYUKI HIROSHIMA, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku
-
Patent number: 9992878Abstract: A circuit board disclosed herein includes: two substrates opposed to each other, where a dielectric being interposed between the two substrates; a through hole formed in each of the two substrates and filled with the dielectric; a first conductor film formed on an inner surface of the through hole; and a second conductor film covering the through hole on a main surface of each of the two substrates on an opposite side to the dielectric, the second conductor film being connected to the first conductor film on the main surface side.Type: GrantFiled: November 2, 2015Date of Patent: June 5, 2018Assignee: FUJITSU LIMITEDInventors: Mitsuhiko Sugane, Akiko Matsui, Takahide Mukoyama, Tetsuro Yamada, Yoshiyuki Hiroshima, Kohei Choraku
-
Publication number: 20170293095Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.Type: ApplicationFiled: June 19, 2017Publication date: October 12, 2017Applicant: FUJITSU LIMITEDInventors: Kohei Choraku, AKIKO MATSUI, Tetsuro Yamada, YOSHIYUKI HIROSHIMA
-
Publication number: 20170290144Abstract: A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.Type: ApplicationFiled: March 22, 2017Publication date: October 5, 2017Applicant: FUJITSU LIMITEDInventors: YOSHIYUKI HIROSHIMA, AKIKO MATSUI, Mitsuhiko Sugane, Takahide Mukoyama, Tetsuro Yamada, Kohei Choraku