Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: A light emitting apparatus includes a light emitting element, a temperature measurement device, a driving control unit, a calculation unit configured to calculate a correction value of a driving control parameter based on a measured temperature; and a change unit configured to change a coefficient of a function based on the measured temperature. The calculation unit calculates the correction value with respect to the measured temperature based on a function obtained by expressing a first function, which expresses a relationship between the measured temperature and the correction value, by a combined function of a plurality of third functions each generated by changing a coefficient of a second function, and the change unit changes, based on the measured temperature, the coefficient of the second function to generate the plurality of third functions.

Abstract: A light emitting apparatus includes a light emitting element, a temperature measurement device, a driving control unit, a calculation unit configured to calculate a correction value of a driving control parameter based on a measured temperature; and a change unit configured to change a coefficient of a function based on the measured temperature. The calculation unit calculates the correction value with respect to the measured temperature based on a function obtained by expressing a first function, which expresses a relationship between the measured temperature and the correction value, by a combined function of a plurality of third functions each generated by changing a coefficient of a second function, and the change unit changes, based on the measured temperature, the coefficient of the second function to generate the plurality of third functions.

Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: A bus control circuit comprises an arbitration circuit which receives a bus-transfer request from each of a plurality of bus masters and outputs an arbitration result signal, in accordance with a priority order, to one of the bus masters, and a plurality of bus switches, wherein each bus switch comprises a selection circuit which includes a plurality of input terminals for receiving a plurality of bus transfer signals and an output terminal for transmitting one bus transfer signal to a downstream side, and a control circuit which receives the arbitration result signal from the arbitration circuit and controls the selection circuit based on the arbitration result signal to select one of the plurality of input terminals, and a slave module is connected to the output terminal of the selection circuit in the bus switch located at a most downstream position.

Abstract: A bus control circuit comprises an arbitration circuit which receives a bus-transfer request from each of a plurality of bus masters and outputs an arbitration result signal, in accordance with a priority order, to one of the bus masters, and a plurality of bus switches, wherein each bus switch comprises a selection circuit which includes a plurality of input terminals for receiving a plurality of bus transfer signals and an output terminal for transmitting one bus transfer signal to a downstream side, and a control circuit which receives the arbitration result signal from the arbitration circuit and controls the selection circuit based on the arbitration result signal to select one of the plurality of input terminals, and a slave module is connected to the output terminal of the selection circuit in the bus switch located at a most downstream position.

Abstract: A memory controller is capable of issuing a first write command for writing data of a predetermined size in a DRAM, and a second write command for writing data of a size smaller than the predetermined size in the DRAM. The memory controller comprises a receiving unit configured to receive a request to the DRAM from a bus; a determining unit configured to determine whether a command that is after the second write command when a reception sequence of a request is observed is issuable in a period until the second write command is issued after a preceding command is issued; and an issuing unit configured to issue a command determined to be issuable before the second write command.

Abstract: A display system includes a master device that displays a master image corresponding to a part of image data, and a slave device that displays a slave image corresponding to another part of the image data. The slave device includes a slave signal generation unit that starts to generate a slave timing signal at a predetermined interval with reference to a timing based on a first instruction received from the master device, a slave communication unit that transmits to the master device a completion notification indicating that a preparation for displaying the slave image is completed, and a slave display unit that displays the slave image in synchronization with the slave timing signal corresponding to a second instruction received from the master device.

Abstract: A display system includes a master device that displays a master image corresponding to a part of image data, and a slave device that displays a slave image corresponding to another part of the image data. The slave device includes a slave signal generation unit that starts to generate a slave timing signal at a predetermined interval with reference to a timing based on a first instruction received from the master device, a slave communication unit that transmits to the master device a completion notification indicating that a preparation for displaying the slave image is completed, and a slave display unit that displays the slave image in synchronization with the slave timing signal corresponding to a second instruction received from the master device.

Abstract: An image processing apparatus reads an image out of a frame buffer by vertically flipping the image, writes the image into an output line buffer by horizontally flipping the image, divides each line, and simultaneously outputs the resulting line segments. Methods for vertical flipping, horizontal flipping, and simultaneous output are changed according to the output settings.

Abstract: An image processing apparatus reads an image out of a frame buffer by vertically flipping the image, writes the image into an output line buffer by horizontally flipping the image, divides each line, and simultaneously outputs the resulting line segments. Methods for vertical flipping, horizontal flipping, and simultaneous output are changed according to the output settings.

Abstract: A timing control apparatus includes: an extraction unit that outputs an input timing signal of an image signal; an input timing switch unit that selects whether to output the input timing signal output from the extraction unit or to input an external input timing signal; an input timing delay addition unit capable of adding delay information to the input timing signal output from the extraction unit; a reference timing generation unit that generates a reference timing signal from the input timing signal; a reference timing switch unit that selects whether to output the reference timing signal or to input an external reference timing signal; and an individual timing generation unit that generates, from the reference timing signal, a video processing timing signal and an output timing signal.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: A projection apparatus capable of projecting an image with a user interface screen superimposed thereon includes a detection unit configured to detect a distortion amount of the image, a calculation unit configured to calculate a parameter for correcting the image based on the distortion amount detected by the detection unit, and a determination unit configured to determine a shape of the user interface screen based on the parameter.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.

Abstract: A memory controller determines a load level based on the number of connected memory devices informed by a switch or the like. If it is determined that the load level is high, the memory controller increases the number of cycles for issuing command/address signals, and if it is determined that the load level is low, the memory controller reduces the number of issuing cycles.

Abstract: In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the plurality of slave ports, an address phase that issues an address and a command and a data phase that issues write data are separated, and an address phase of next transaction can be issued before the data phase is completed. This improves performance of a system, in which a plurality of master modules and slave modules are connected through the bus.