Patents by Inventor Kohei Sugihara

Kohei Sugihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020163036
    Abstract: A field-effect transistor including a gate electrode, silicon layers and source/drain regions is formed at a surface of a silicon substrate. Sidewall insulating films formed on the opposite side surfaces of the gate electrode are provided at portions located between the gate electrode and the silicon layers with voids, respectively. A semiconductor device having a field-effect transistor capable of fast operation is formed.
    Type: Application
    Filed: September 18, 2001
    Publication date: November 7, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naruhisa Miura, Toshiyuki Oishi, Yuji Abe, Kohei Sugihara
  • Publication number: 20020158292
    Abstract: A semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof are obtained. The semiconductor device includes source and drain regions of first conductivity type disposed to sandwich a channel region, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of side surface parts of the source and drain regions on the channel region side and respectively form a junction only between the neighborhood of the side surface parts and the pocket injection regions.
    Type: Application
    Filed: June 19, 2002
    Publication date: October 31, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
  • Publication number: 20020045317
    Abstract: Source/drain regions are formed with two regions of an epitaxial silicon film formed on the surface of the substrate and a region formed by ion implantation and thermal diffusion of impurities into the substrate, and the depth of junction of the source/drain regions is formed at a depth identical with or shallower than the depth of junction of the extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source/drain regions is predominant, the short channel effect are less degraded.
    Type: Application
    Filed: September 19, 2001
    Publication date: April 18, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiyuki Oishi, Kohei Sugihara, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
  • Publication number: 20020037619
    Abstract: A dummy gate electrode is formed before the gate electrode is formed. Extension regions, side wall silicon nitride film, source/drain regions, silicon oxide film, and others are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused to a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method gives a semiconductor device that prevents the deterioration of electrical characteristics caused by short channel effect and parasitic resistance.
    Type: Application
    Filed: March 16, 2001
    Publication date: March 28, 2002
    Inventors: Kohei Sugihara, Toshiyuki Oishi, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
  • Publication number: 20020011635
    Abstract: A semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof are obtained. The semiconductor device includes source and drain regions of first conductivity type disposed to sandwich a channel region, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of side surface parts of the source and drain regions on the channel region side and respectively form a junction only between the neighborhood of the side surface parts and the pocket injection regions.
    Type: Application
    Filed: December 14, 2000
    Publication date: January 31, 2002
    Inventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
  • Patent number: 6228728
    Abstract: According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: May 8, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Takumi Nakahata, Shigemitsu Maruno, Kohei Sugihara, Yasutaka Nishioka, Satoshi Yamakawa, Yasunori Tokuda