Abstract: A photoelectric converter includes a pixel array including a plurality of pixels, a capacitive coupling amplifier configured to amplify a signal output from the pixel array, and a delta-sigma AD converter configured to convert, into a digital signal, an analog signal output from the amplifier. The amplifier is formed by a plurality of first elements including an active element and a capacitive element. The delta-sigma AD converter is formed by a plurality of second elements including an active element and a capacitive element. A breakdown voltage of at least one of the plurality of second elements forming the delta-sigma AD converter is lower than a breakdown voltage of the plurality of first elements forming the amplifier.

Abstract: A photoelectric conversion apparatus includes a light receiving circuit configured to convert light into an electrical signal, a readout circuit configured to read out an analog signal corresponding to the electrical signal, a ?? A/D converter configured to convert the analog signal into a digital signal, and a control circuit configured to change a gain of the photoelectric conversion apparatus in accordance with a change of a driving mode of the photoelectric conversion apparatus. The analog signal read out by the readout circuit is an analog current signal. The readout circuit includes a variable resistor on a signal path for supplying the analog current signal to the ?? A/D converter. The control circuit changes the gain of the photoelectric conversion apparatus by changing a resistance value of the variable resistor.

Abstract: A photoelectric converter includes a structure in which a first substrate and a second substrate are stacked, wherein a pixel array including a plurality of pixels is arranged on the first substrate, and at least part of a sample-and-hold circuit configured to sample and hold a signal output from the pixel array is arranged on the first substrate, and wherein at least part of a delta-sigma AD converter configured to convert an analog signal output from the sample-and-hold circuit into a digital signal is arranged on the second substrate.

Abstract: A photoelectric conversion apparatus includes a second substrate including a signal processing circuit configured to perform signal processing using machine learning on a signal output from the first substrate. The second substrate is disposed on the first substrate in a multilayer structure. The signal processing circuit is so disposed to overlap with a pixel array but not overlap with a light-shielded pixel area as seen in a plan view.

Abstract: An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

Abstract: An AD conversion circuit includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a result of the comparison, and performs an AD conversion using the comparison result signal. In the comparison, a potential of the ramp signal changes with a lapse of time from a first potential to a second potential. Before the comparison, the potential of the ramp signal changes at a first change rate and then changes at a second change rate smaller than the first change rate, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and the comparator is reset in a state where the third potential is input to the comparator.

Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

Abstract: According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.

Abstract: A photoelectric conversion apparatus includes a pixel, an A/D conversion portion and an output circuit. The pixel includes first and second photoelectric conversion portions and an accumulation portion configured to accumulate a signal charge in a location other than the photoelectric conversion portions. The A/D conversion portion is configured to perform A/D conversions on signals based on signal charges generated in the photoelectric conversions. The output circuit reads out first and second signals based on first and second signal charges accumulated in the first and second photoelectric conversion portions during an electric charge accumulation period and a third signal based on a third signal charge generated in the second photoelectric conversion portion and accumulated in the accumulation portion during the electric charge accumulation period. Conversion periods for analog-to-digital conversion to be performed on at least two of the first, second, or third signals have different lengths.

Abstract: Provided is an imaging device including: a photoelectric converter; an AD converter unit including a differential stage; and a ramp signal generator. The photoelectric converter and a first part of the differential stage are arranged in a first chip, a second part of the differential stage is arranged in a second chip that is a different chip from the first chip and stacked on the first chip, and the ramp signal generator is arranged in a different chip from the first chip.

Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

Abstract: An AD conversion circuit includes a comparator configured to compare an analog signal with a ramp signal and output a comparison result signal indicating a result of the comparison, and performs an AD conversion using the comparison result signal. In the comparison, a potential of the ramp signal changes with a lapse of time from a first potential to a second potential. Before the comparison, the potential of the ramp signal changes at a first change rate and then changes at a second change rate smaller than the first change rate, the potential of the ramp signal changes from the first potential to a third potential between the first potential and the second potential, and the comparator is reset in a state where the third potential is input to the comparator.

Abstract: An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.

Abstract: An imaging device includes a first chip on which a plurality of first blocks is arranged in a matrix, and a second chip which includes a first block scanning circuit and a second block scanning circuit. The second chip includes a selection circuit configured to select driving timing given to a plurality of pixels, based on a signal output from the first block scanning circuit and a signal output from the second block scanning circuit. A second block includes a circuit other than the selection circuit.

Abstract: A solid-state imaging device includes a plurality of pixels, a reference signal supply unit configured to output a reference signal, and a comparison unit configured to output a signal depending on the reference signal and a signal from the pixel. The comparison unit includes a comparator circuit including an input terminal and an output terminal, a first switch configured to connect the input terminal and the output terminal of the comparator circuit, a clamp capacitor including a first terminal connected to the input terminal of the comparator circuit, a second switch connected to a second terminal of the clamp capacitor, and configured to select one of the signal from the pixel and the reference signal and to input the selected signal to the second terminal, and a clipping circuit arranged in an electrical path through which the reference signal is input to the comparator circuit.

Abstract: According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.

Abstract: A semiconductor apparatus of the present disclosure includes: a first semiconductor component in which a first circuit unit is provided; and a second semiconductor component in which a second circuit unit is provided and which is stacked to the first semiconductor component, and the second semiconductor component includes a capacitor unit as a decoupling capacitor having a first node and a second node that are connected to the first circuit unit.

Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

Abstract: A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

Abstract: An imaging device including an operation signal generation circuit of reduced circuit scale is provided. The imaging device includes a selection circuit configured to output a pixel transfer pulse signal to be input to a gate of a transfer transistor of a pixel based on a vertical block control signal, a horizontal block control signal, and a row transfer pulse signal.