Patents by Inventor Kohichi Tanaka

Kohichi Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8717340
    Abstract: Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 6, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshio Mizuki, Akihiko Kohno, Kohichi Tanaka
  • Publication number: 20130087802
    Abstract: It is an object to increase the mobility of a thin film transistor having an active layer including a microcrystalline semiconductor film. Upon fabricating an inverted staggered type TFT 10, a substrate is vacuum-transferred to a plasma enhanced CVD apparatus such that a surface of a microcrystalline silicon film (active layer 40) exposed by gap etching is not exposed to the air. An insulating film 80 is deposited by the plasma enhanced CVD apparatus so as to completely cover the exposed surface of the microcrystalline silicon film. By this, even if the microcrystalline silicon film is exposed to the air, oxygen cannot be adsorbed on the surface thereof and thus diffusion of oxygen into the microcrystalline silicon film can be suppressed. In addition, since N+ silicon films composing contact layers 50a and 50b directly contact with the microcrystalline silicon film, the contact resistance can be reduced.
    Type: Application
    Filed: March 25, 2011
    Publication date: April 11, 2013
    Inventors: Akihiko Kohno, Toshio Mizuki, Kohichi Tanaka
  • Publication number: 20120287094
    Abstract: Disclosed is a thin film transistor that is provided with a gate insulating film that is inexpensive, and that is less likely to have a low-density microcrystalline silicon layer formed thereon due to plasma induced damage, while suppressing fluctuation of a threshold voltage. In a TFT (100) having the bottom gate structure, since a silicon nitride film (31) having a natural oxide film (32) formed on the surface thereof is used as the gate insulating film (30), the gate insulating film (30) is not only capable of preventing the alkali metal ions contained in a glass substrate (10) from entering the gate insulating film (30), but also capable of suppressing a formation of the low-density microcrystalline silicon layer on the surface of a microcrystalline silicon film (41) on the side in contact with the gate insulating film (30). Since the mobility of the microcrystalline silicon film (41) is increased, the operation speed of the TFT (100) can be improved.
    Type: Application
    Filed: October 20, 2010
    Publication date: November 15, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Toshio Mizuki, Akihiko Kohno, Kohichi Tanaka
  • Publication number: 20120193633
    Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate (11a) in a chamber (26); (b) supplying a microwave into the chamber (26) through a dielectric plate (24), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film (14) with an aluminum concentration of 1.0×1016 atoms/cm3 or less on the substrate (11a) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm2/Vs as its active layer is obtained.
    Type: Application
    Filed: September 21, 2010
    Publication date: August 2, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Akihiko Kohno, Toshio Mizuki, Kohichi Tanaka
  • Patent number: 7642399
    Abstract: The present invention provides a GLAST knockout mouse lacking the function of an endogenous glutamate transporter GLAST gene, which shows: 1) an intraocular pressure within the normal range; and 2) a reduction in the number of cells in the retinal ganglions when compared with a wild-type normal mouse. Owing to the ocular properties, this knockout mouse is useful as a model for normal tension glaucoma. By using this knockout mouse, a compound useful for the treatment of normal tension glaucoma can be screened.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: January 5, 2010
    Assignee: Japan Science and Technology Agency
    Inventors: Kohichi Tanaka, Takayuki Harada
  • Publication number: 20070011758
    Abstract: The present invention provides a GLAST knockout mouse lacking the function of an endogenous glutamate transporter GLAST gene, which shows: 1) an intraocular pressure within the normal range; and 2) a reduction in the number of cells in the retinal ganglions when compared with a wild-type normal mouse. Owing to the ocular properties, this knockout mouse is useful as a model for normal tension glaucoma. By using this knockout mouse, a compound useful for the treatment of normal tension glaucoma can be screened.
    Type: Application
    Filed: April 13, 2004
    Publication date: January 11, 2007
    Inventors: Kohichi Tanaka, Takayuki Harada
  • Patent number: 5972536
    Abstract: A negative electrode material for a secondary cell for anon-aqueous liquid electrolyte for realizing a high charging/discharging capacity and a high discharging efficiency, a method for producing such material and a non-aqueous liquid electrolyte secondary cell employing such material. The negative electrode material contains at least one carbonaceous material selected from the group consisting of coffee beans, tea leaves, cane sugar, corns, fruits, straws of cereals and husks of cereals, a carbonaceous material derived from a plant-origin high molecular material containing a sum total of 0.2 to 20 wt % of metal elements, phosphorus and sulphur calculated as elements or a carbonaceous material having a diffraction peak between 30.degree. and 32.degree. of the 2.theta. diffraction angle in the X-ray (CuK.alpha.) powder diffraction pattern.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 26, 1999
    Assignee: Sony Corporation
    Inventors: Shinichiro Yamada, Hiroyuki Akashi, Hiroshi Imoto, Hideto Azuma, Kenichi Kitamura, Momoe Adachi, Terue Sasaki, Kohichi Tanaka
  • Patent number: 5834138
    Abstract: A negative electrode material for a secondary cell for a non-aqueous liquid electrolyte for realizing a high charging/discharging capacity and a high discharging efficiency, a method for producing such material and a non-aqueous liquid electrolyte secondary cell employing such material. The negative electrode material contains at least one carbonaceous material selected from the group consisting of coffee beans, tea leaves, cane sugar, corns, fruits, straws of cereals and husks of cereals, a carbonaceous material derived from a plant-origin high molecular material containing a sum total of 0.2 to 20 wt % of metal elements, phosphorus and sulphur calculated as elements or a carbonaceous material having a diffraction peak between 30.degree. and 32.degree. of the 2.theta. diffraction angle in the X-ray (CuK.alpha.) powder diffraction pattern.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: November 10, 1998
    Assignee: Sony Corporation
    Inventors: Shinichiro Yamada, Hiroyuki Akashi, Hiroshi Imoto, Hideto Azuma, Kenichi Kitamura, Momoe Adachi, Terue Sasaki, Kohichi Tanaka
  • Patent number: 5718620
    Abstract: A polishing machine for polishing a flat workpiece such as a semiconductor wafer has a rotatable reference table supporting an abrasive cloth disposed on a surface thereof, and a rotatable workpiece holder for holding a flat workpiece against the abrasive cloth. While the flat workpiece is being polished by the abrasive cloth, an abrasive compound is supplied between the abrasive cloth and the flat workpiece. The reference table has grooves defined therein for dissipating heat from the reference table and the abrasive cloth while the flat workpiece is being polished by the abrasive cloth. The grooves may be supplied with either the abrasive compound or a coolant.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: February 17, 1998
    Assignee: Shin-Etsu Handotai
    Inventors: Kohichi Tanaka, Hiromasa Hashimoto, Fumio Suzuki
  • Patent number: 5549502
    Abstract: A grinding method and apparatus having a position aligning mechanism to correctly achieve the centering of each work on a work table and locate an orientation flat part of each work at a predetermined position, and a displacing mechanism for reciprocally slidably displacing a top ring and the work table in order to assure that the center of each work is positionally aligned with the center of each top ring at an original position after completion of the centering of each work on the work table and the locating of the orientation flat part, and subsequently, centering each top ring with the gravitational center of each work so as to cancel a positional offset state prior to holding the work with the top ring to thrust the work against the grinding or polishing surface. The invention also includes a polishing method and apparatus in which both of a top ring and a rotary disc are reciprocally slidably displaced to improve the polishing efficiency of the device.
    Type: Grant
    Filed: December 6, 1993
    Date of Patent: August 27, 1996
    Assignees: Fujikoshi Machinery Corp., Shin-Etsu Handotai Co., Ltd.
    Inventors: Kohichi Tanaka, Hiromasa Hashimoto, Yasuo Inada, Makoto Nakajima
  • Patent number: 5400547
    Abstract: A polishing machine for polishing a flat workpiece such as a semiconductor wafer has a rotatable reference table supporting an abrasive cloth disposed on a surface thereof, and a rotatable workpiece holder for holding a flat workpiece against the abrasive cloth. While the flat workpiece is being polished by the abrasive cloth, an abrasive compound is supplied between the abrasive cloth and the flat workpiece. The reference table has grooves defined therein for dissipating heat from the reference table and the abrasive cloth while the flat workpiece is being polished by the abrasive cloth. The grooves may be supplied with either the abrasive compound or a coolant.
    Type: Grant
    Filed: February 25, 1993
    Date of Patent: March 28, 1995
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kohichi Tanaka, Hiromasa Hashimoto, Fumio Suzuki
  • Patent number: 5335457
    Abstract: A method of chucking semiconductor wafers, in which a silicone elastic layer with high flatness is formed on the surface of a hard substrate having fine through-holes for vacuum chucking. Next fine through-holes in the silicone elastic layer, are provided, each through-hole communicating with the fine through-holes of the hard substrate. Next a semi-conductor wafer is held on the hard substrate by vacuum chucking from the back side of the substrate, so as to hold the semiconductor wafer securely on the substrate only by surface adhesion of the silicone elastic layer during polishing of the wafer. This method does not require wax or similar adhesive for holding the semiconductor wafer on the hard surface during the polishing process, and can realize a high-precision and high-quality surface polishing process for the semiconductor wafers.
    Type: Grant
    Filed: October 26, 1992
    Date of Patent: August 9, 1994
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Akira Matsuda, Shigeki Shudo, Noboru Shimamoto, Kohichi Tanaka, Hiromasa Hashimoto, Fumio Suzuki
  • Patent number: 5226758
    Abstract: A semiconductor wafer handling apparatus and method for transferring a wafer, one of whose faces has been already polished, from a wafer holder, which holds the wafer with the wafer's polished face facing downward, to a wafer cassette submerged in water contained in a water tank; the apparatus includes a wafer receive assembly and a water tank and the wafer receive assembly has a flat surface and is adapted to swing between an up-facing position at which the flat surface faces upward and a down-facing position at which the flat surface faces downward, and the wafer receive assembly is provided with ejection nozzles which eject water with a force sufficient to keep the wafer floating, and the water tank contains a wafer cassette to receive the wafer, and is capable of forcing the wafer which is left to sink in the water to enter the wafer cassette; whereas the method comprises: dropping the wafer from the wafer holder with the polished face facing downward onto a thin water layer formed over the wafer receive
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: July 13, 1993
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kohichi Tanaka, Makoto Tsukada, Fumio Suzuki